AWS unveils Ocelot, its first quantum computing chip

For quantum computers to solve problems in materials design, quantum chemistry and cryptography, in which known speed-ups relative to classical computations are attainable, currently proposed algorithms require trillions of qubit gate operations to be applied in an error-free manner. Despite impressive progress over the past few decades in reducing qubit error rates at the physical hardware level, the state-of-the-art remains about nine orders of magnitude away from these requirements. A path towards closing the error-rate gap is through quantum error correction (QEC) which can exponentially suppress errors through the redundant encoding of information across many noisy physical qubits.

Recently, QEC experiments have been performed in various hardware platforms, including superconducting quantum circuits trapped ions and neutral atoms. Some of these experiments are approaching, or have surpassed, the threshold at which scaling of the error-correcting code size leads to exponential improvements in the logical qubit error rate. In these experiments, the qubits are realized using a simple encoding into two levels of a physical element, leaving them susceptible to environmental noise that can cause both bit and phase-flip errors. Correcting for both types of error requires QEC codes such as the surface code which have a relatively high overhead penalty.

Alternatively, we can use a layered approach to noise protection by starting from an encoded qubit that natively suppresses errors. An example is bosonic qubits, in which qubit states are encoded in the infinite-dimensional Hilbert space of a bosonic mode (a quantum harmonic oscillator) using bosonic QEC. In bosonic QEC, the large oscillator Hilbert space is exploited to suppress errors. Experiments demonstrating this exploitation at the single bosonic mode level have been performed using cat codes binominal codes and GKP codes. At the same time, various proposals have been put forward to further scale bosonic QEC by concatenating it with an outer code across multiple bosonic modes leveraging the protection offered in each bosonic mode to reduce the overall resource overhead for QEC.

In this work, we demonstrate a scalable, hardware-efficient logical qubit memory built from a linear array of bosonic modes using a variant of the repetition cat code proposal in ref. In particular, we stabilize noise-biased cat qubits in individual bosonic modes. Bit-flip errors of the cat qubits are natively suppressed at the physical level, and the remaining phase-flip errors are corrected by an outer repetition code. The use of a repetition code enables low overhead because of its large error rate threshold and linear scaling of code distance with physical qubit number. In what follows, we describe a microfabricated superconducting quantum circuit that realizes a distance d = 5 repetition cat code logical qubit memory, present a noise-biased CX gate for implementing error syndrome measurements with ancilla transmons and study the logical qubit error correction performance.

Quantum device realizing a distance-5 repetition code

A schematic of our repetition code device and the corresponding superconducting circuit layout. The distance d = 5 repetition code consists of five bosonic modes that host the data qubits (blue), along with four ancilla qubits (orange). The bosonic modes, also referred to as storage modes, are coplanar waveguide resonators with an average T₁ time of more than 60 μs and an average T₂ time of more than 80 μs. The ancilla qubits are fixed-frequency transmons and are coupled to the storage modes by tunable-transmon couplers that realize a tunable dispersive coupling (see ref. and Supplementary Information). This dispersive interaction is used for a controlled-X operation (CX gate), with the ancilla transmon as the control and the data qubit as the target. Using the CX gates, we measure the repetition code stabilizers X^iX^i+1 (grey triangles), equivalent to measuring the joint photon-number parity of two neighbouring storage modes. Each ancilla qubit can be read out and reset through a readout resonator

Each data qubit in our system is a cat qubit encoded in storage mode. The basis states of a cat qubit are along with their experimental Wigner tomograms. The |0⟩ and |1⟩ computational basis states are approximately the |α⟩ and |−α⟩ coherent states, respectively, with a mean photon number of ∣α∣². The complementary basis states are exactly the even and odd cat states |±⟩ ∝ |α⟩ ± |−α⟩. Thus, a bit-flip (X) error is a 180° rotation in the phase space mapping |α⟩ ↔ |−α⟩, and a phase-flip (Z) error corresponds to a parity flip between the even and odd cat states. Owing to the phase-space separation of the |±α⟩ coherent states, bit-flip error rates can be exponentially suppressed with cat size ∣α∣². By contrast, phase-flip errors, which are caused by single-photon loss and heating, have a rate that increases linearly with ∣α∣².

To ensure that their noise bias is maintained over time, the cats are stabilized using two-photon dissipation, confining them to the |±α⟩ manifold. To realize the two-photon dissipation, we nonlinearly couple each storage mode to a lossy buffer mode (green), which is implemented using a version of the asymmetrically threaded SQUID element Our buffer mode implementation ensures that the storage-mode lifetime and linearity are not degraded by the coupling to the lossy and nonlinear buffer Supplementary Information).

Figure shows the bit-flip and phase-flip times of all five data cat qubits when they are being simultaneously stabilized by two-photon dissipation. Over the range of ∣α∣² considered, the bit-flip times of our cat qubits increase exponentially with the mean photon number ∣α∣². As expected, the phase-flip times degrade as T_1,eff/∣α∣², where the effective storage lifetimes under two-photon dissipation, T_1,eff, are in the range 57–68 μs. A particularly important feature of our cat qubits is that a large noise bias is achieved even with small values of ∣α∣². Concretely, at ∣α∣² = 2, we achieve greater than 1 ms bit-flip times and 27–33 μs phase-flip times. This constitutes a sizable (>30) noise bias and at the same time a long phase-flip time in comparison to an error correction cycle time (2–3 μs).

Conclusion and outlook

In this work, we have performed error correction using a concatenated bosonic code, in which bit-flip errors are suppressed with a bosonic cat code and residual phase-flip errors are corrected with a repetition code. This experiment serves as a promising first step in taking advantage of bosonic qubits, and also noise bias, to improve the hardware efficiency of QEC. Furthermore, having constructed our logical qubit memory using planar microfabrication processes, this work highlights the potential scalability of the concatenated bosonic qubit architecture.

The logical error in our current device is dominated by intrinsic cat bit-flip and phase-flip errors, but there are several strategies to reduce these errors in the near term. We project that by optimizing cycle time and using the further optimized cat qubit circuit, an overall logical error per cycle approaching 0.5% (limited by transmon errors) is achievable with a distance-5 code even without improvements in the component coherence times.

The use of ancillary transmons for syndrome measurements is important to our experiment, enabling noise-biased CX gates without undesired control errors, but comes along with ancilla-induced bit-flip errors. The logical performance at present is not limited by these errors, and improved ancilla lifetimes of 1 ms would ideally lower their probability to about 10⁻⁶ per CX (Supplementary Information). However, in the long term, it will be necessary to eventually correct ancilla-induced bit flips, which can be accomplished by concatenating cat qubits into surface codes tailored to noise-biased qubits. We analyse this approach and find that marked hardware-efficiency improvements are possible relative to the case without biased noise.

An alternative approach to overcome the transmon-induced limitations is to use cat qubits as the ancillas. This was proposed but existing proposals for cat–cat CX gates are hampered by large control errors. Searching for ways to implement syndrome measurements with a large noise bias but without undesired control errors thus represents an important direction for future research. If the performance of gates were limited only by the intrinsic bit-flip and phase-flip rates of the cats, sizable reductions in logical-memory overhead would be possible with realistic device parameters. For example, with the cat qubit bit-flip times, we show and improved storage lifetimes of about 300 μs we project (Supplementary Information) that ϵ_L ~ 10⁻⁵ could be achieved with a d = 11 repetition cat code. Furthermore, with ≳100 s bit-flip times and ms-scale storage T₁  algorithmically-relevant ϵ_L ~ 10⁻⁸ could be achieved with similar overhead. Although these examples assuming coherence-limited gates are idealized hypotheticals, they nevertheless highlight the potential of cat qubits to enable hardware-efficient logical qubits.