Broadcom discusses its co-packaged optics plans

If electrical interfaces are becoming an impediment, is co-packaged optics the answer? Broadcom certainly thinks so.

One reason for the growing interest in co-packaged optics is the input-output (I/O) demands of switch chips. If the packet processing capacity of such chips is doubling every two years, their I/O must double too.

But repeatedly doubling the data throughput of a switch chip is challenging.

Each new generation of switch chip must either double the number of serialiser-deserialiser (serdes) circuits or double their speed.

A higher serdes count – the latest 25.6-terabit switch ICs have 256, 100 gigabit-per-second serdes – requires more silicon area while both approaches – a higher count and higher speed – increase the chip’s power consumption.

Faster electrical interfaces also complicate the system design since moving the data between the chip and the optical modules on the switch’s front panel becomes more challenging.

Brad Booth, director, edge architecture pathfinding team in Azure hardware systems and infrastructure at Microsoft, and president of the Consortium of On-Board Optics (COBO), describes the issue of electrical interfaces as a massive impediment.

“How do we move forward with what we need to keep the bandwidth-density growing on these devices?” says Booth. “That is not going to be solved with electronics anymore.”

This explains why co-packaged optics is getting so much attention and why standardisation efforts have been started by COBO and by the OIF.