Faraday Technology collaborated with Infineon Technologies AG to develop a SONOS eFlash platform on UMC’s 40uLP process.
This platform includes a newly developed eFlash subsystem IP and complete eFlash testing solution with easy-to-integrate and fast data access features. This total solution facilitates customers to accelerate product development and utilize the flash memory technology more easily; meanwhile, it also simplifies SONOS eFlash testing with a built-in self-test (BIST) function to provide customers quality advantages.
To meet the demand for 40nm low-power and secure eFlash driven by AI, smart grid, IoT, and MCU applications, Faraday and Infineon jointly developed this SONOS eFlash platform. This platform mainly contains a flash memory block, controller and the new subsystem IP. This subsystem includes essential bus interface, integrated clock control circuits and additional features, such as automatic eFlash initialization, simplified erase/write procedure to offload CPU overhead, RW protection, and a pseudo random write buffer, for IP integration and utilization of SONOS eFlash IP. In addition, this subsystem with BIST enables the chips to be tested on general testing equipment to ensure the flash memory quality and reliability, as well for testing time reduction.
“We are excited to work with Faraday to develop this SONOS eFlash platform for customers,” said Vineet Agrawal, senior director, memory solutions, Infineon Technologies. “The 40uLP SONOS eFlash has already delivered abundant mass-production projects within the last few years. With Faraday’s comprehensive SONOS eFlash IP subsystem, IP portfolio, and testing solutions, we believe this solution will facilitate Faraday’s customers to speed up the development of a wide range of high-performance and low-power products in the near future.”
“Infineon’s SONOS eFlash technology has been market-proven in various applications on 40nm process,” said Flash Lin, COO, Faraday. “By leveraging the advantages of Infineon’s SONOS eFlash on UMC 40uLP, manufacturing cycle time can benefit from far fewer additional mask layers when compared to other eFlash solutions. Combining with the new platform and our comprehensive ready-to-use 40nm IP products, which are fully compatible with 40uLP SONOS eFlash process, we further help customers easily achieve cost, power, and performance requirements for their next-generation designs.”