Global Unichip (GUC), the advanced ASIC leader, announced that they have silicon proved 8.4 Gbps HBM3 solution on TSMC’s 5nm process technology. The platform was demonstrated at the Partner Pavilion of the TSMC 2023 North America Technology Symposium. It contains full functional HBM3 Controller and PHY IP and vendor’s HBM3 memory using TSMC’s CoWoS® technology.
HBM memory vendors keep aggressive roadmap increasing throughput and memory size from HBM3 to HBM3E/P and further doubling data bus width at HBM4. But fundamental DRAM timing parameters don’t change and HBM Controller is getting more and more sophisticated to enable full bus utilization. GUC’s HBM3 Controller achieves above 90% bus utilization at random access while keeping low latency. GUC’s HBM3 PHYs are silicon proven at TSMC’s 5nm technology and were taped out at the TSMC 3nm early this year, and ready to support the fastest planned HBM3E/P memories. The PHYs are verified with angle routing of HBM bus on both CoWoS-S and CoWoS-R interposers enabling offsetting HBM PHY vs. HBM memory for ASIC floorplaning flexibility. GUC’s HBM Controller and PHY IPs are used in customers’ HPC ASICs for production since 2020.
Explosion in amount of computation required from Level4 Autonomous Driving computer leads to adoption of 2.5D chiplet-based architectures and HBM3 memories by car processors. Harsh car environment and high reliability requirement make continuous monitoring of 2.5D interconnect and replacement of failing lanes necessary. GUC integrates proteanTecs’ health and performance monitoring solutions into all its HBM and die-to-die interface test chips. proteanTecs’ technology is now silicon proven in GUC’s 5nm HBM3 PHY, up to 8.4 Gbps. During data transfer in mission mode, I/O signal quality is continuously monitored, without any re-training or interruptions. Each signal lane is individually monitored, allowing for the identification and repair of bump and trace defects before they cause system operational failures and therefore extending the chip’s lifetime. “We are proud to demonstrate the world’s first HBM3 controller and PHY at 8.4 Gbps,” said Dr. Sean Tai, president of GUC. “We established a complete 2.5D/3D chiplet IP portfolio at TSMC’s 7nm, 5nm and 3nm technologies. Together with design expertise on the TSMC 3DFabric™ technologies including CoWoS, InFO, and TSMC-SoIC, we provide our customers robust and comprehensive solution of their AI/HPC/xPU/Networking/ADAS products.”
“Based on high-volume manufacturing experience of our 2.5D chiplet products we defined the strictest qualification cycle and covered our IPs with comprehensive set of diagnostics, it allows our IPs to pass the toughest quality criteria of the car manufacturers.” said Igor Elkanovich, CTO of GUC. “Convergence of 2.5D and 3D packaging using HBM3, GLink-2.5D/UCIe and GLink-3D interfaces enables highly modular, chiplet-based, much- bigger-than-reticle-size processors of the future.”