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Intel brings chiplets to data center CPUs

By Sally Ward-Foxton for EETIMES – Intel Corp.’s fourth-generation Xeon processor, codenamed Sapphire Rapids, consists of four chiplets, the company revealed during its Architecture Day event.

This marks the first time Intel has integrated chiplets into its Xeon data center CPU line, having previously added the technology to its Stratix 10 FPGA line last year. Stratix 10 was the first product to incorporate Intel’s advanced packaging technology, embedded multi-die interconnect (EMIB), that uses a silicon interposer to connect dies. Previously, Intel combined its CPUs with an AMD GPU in a product called Kaby Lake-G, which did not use EMIB. Intel has also developed vertical die stacking technology called Foveros (used in its Lakefield line), but confirmed this week it will not be used in Sapphire Rapids.

In a pre-Architecture Day interview with EE Times, Intel’s chief engineer for Sapphire Rapids, Nevine Nassif, cited cost and yield advantages enabled by EMIB as the impetus behind the chiplet strategy.

Nevine Nassif

“We started looking at this a long time ago, 15-16 years ago, but what we didn’t have at that time was EMIB technology,” Nassif said. “In the past, whenever we tried breaking a design into two dies, the overhead area you needed for the [interconnect] was too big – that power between the dies was too big, and the latencies would kill performance.”

EMIB has enabled Intel to scale down to 55-micron bump pitch, meaning the overhead for adding die-to-die interconnect has decreased sufficiently while latency is reduced to manageable levels… Full article

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