UMC launches W2W 3D IC project with partners, targeting growth in edge AI

United Microelectronics Corporation (“UMC”), a leading global semiconductor foundry, today announced it has initiated the W2W (wafer-to-wafer) 3D IC project in collaboration with partners Winbond, Faraday, ASE, and Cadence to help customers accelerate production of their 3D products. The project offers an end-to-end solution for integrating memory and processor with silicon stacking technology, catering to the rising demand for efficient computing at the device level as artificial intelligence expands from cloud to the edge.

The W2W 3D IC project with partner collaboration targets edge AI applications – such as home and industrial IoT, security, and smart infrastructure – requiring mid-to-high range computing power, extensive and customizable memory modules, and relatively low power consumption. The platform is expected to be ready in 2024 following the completion of system-level verification, ensuring a seamless process for customers. It will resolve various heterogeneous integration challenges including alignment of wafer stacking rules between logic and memory fabs, effective design flow for vertical wafer integration, and a proven package and testing path.

Each member brings their 3D IC expertise to the project:
UMC – CMOS wafer manufacturing and wafer-to-wafer hybrid bonding technology
Winbond – Introduce Customized Ultra-Bandwidth Elements (CUBE) architecture for powerful edge AI devices, enabling seamless deployment across various platforms and interfaces
Faraday – Comprehensive turnkey services for 3D advanced packaging, as well as memory IP and ASIC chiplets design services
ASE – Die sawing, packaging, and testing services
Cadence – Wafer-to-wafer design flow, extraction with through-silicon vias (TSVs), and sign-off certification

“Through this cross-supply-chain vertically integrated project, we are excited to work with industry leaders to enable customers to leverage our advanced hybrid bonding W2W technology, to enjoy the inherent performance gain, form factor reduction, and cost benefits of 3D IC,” said G C Hung, Vice President of the Result Delivery Office and Research Development at UMC. “Heterogeneous integration will continue to push the boundaries of semiconductor innovation in the More-than-Moore era, and UMC looks forward to contributing our robust CMOS wafer manufacturing capabilities together with advanced packaging solution to the development of a complete ecosystem.”

“As AI continues to move beyond data centers to the edge, edge devices will require higher memory bandwidth in order to handle the increase in data workloads,” said Hsiang-Yun Fan, DRAM Vice President of Winbond. “Winbond is honored to be the memory supplier for this project with our Customized Ultra-Bandwidth Elements (CUBE), which will enable customers to incorporate customized DRAM into their 3D packages for optimal edge AI performance.”

“Faraday is proud to be a founding member of the 3D IC project,” said Flash Lin, COO of Faraday. “We are already working closely with UMC and best-in-class OSAT suppliers for our 2.5D/3D advanced packaging service, and this project is an important extension of that to empower customers in harnessing the endless potential of chip integration.”

“As part of a dynamic ecosystem, ASE is committed to collaborating with industry partners in order to empower our customers to optimize efficiencies in their semiconductor design and manufacturing process,” said Dr. C.P. Hung, Vice President of R&D, ASE. “This project helps us collectively to improve customer time-to-market and sustain profitable growth through the integration technologies developed to accomplish application excellence in the AI era.”

“With the continued proliferation of edge AI applications, 3D IC design is becoming increasingly crucial for our customers. As the only EDA partner in this new project, we’re working closely with Faraday and UMC to enable 3D IC designs with the Cadence Integrity 3D-IC Platform. We are committed to enabling faster time-to-market designs for our customers,” said Don Chan, Vice President, R&D in the Digital & Signoff Group at Cadence.