XConn Technologies (XConn), the innovation leader in next-generation interconnect technology for the future of high-performance computing and AI applications, announced the industry’s first and only hybrid CXL 2.0 and PCIe Gen 5 switch. Combining both Compute Express Link™ (CXL™) technology for next-generation data centers with Peripheral Component Interconnect Express® (PCIe®) Gen 5 interconnect technology on a single 256-lane SoC, the XConn switch offers the industry’s lowest port-to-port latency and lowest power consumption per port in a single chip at a low total cost of ownership.
XConn Technologies is marking the launch of this revolutionary new XC50256 switch, code named “Apollo,” by emerging from “stealth mode” at the Flash Memory Summit this week in Santa Clara, Calif.
The Apollo switch is designed from ground-up and architected purposely for artificial intelligence (AI), machine learning (ML) and HPC applications. System designs using Apollo switch can realize CXL memory pooling and expansion functions with the existing CXL 1.1 hardware, furthermore these designs will be future proofed with the upcoming CXL 2.0 technology. Operating in hybrid mode, the switch supports both CXL and PCIe devices in a same system. This unprecedented flexibility offers system vendors to pick and choose the best components for designing an AI system, while offering a smooth transition from PCIe to CXL in a heterogenous computing environment.
“Our-record breaking Apollo switch sets a new standard in flexibility and performance for next generation of processors and memory,” said Gerry Fan, CEO, XConn. “The release of Apollo underscores our commitment to accelerate AI computing in data centers and HPC applications with the most scalable, most cost efficient and the highest-performance interconnect switch on the market. Apollo is designed to meet both PCIe and CXL requirements in a single chip. The XConn team has been and will continue to work with the industry to accelerate the adoption of CXL and advancement of AI computing.”
XConn is also announcing the availability of a PCIe Gen 5.0-only switch, XC51256. With 256-lanes, this product is the most-dense PCIe Gen 5.0 switch and offers almost twice as many lanes as the nearest competitor. This switch is ideal for the JBOG (Just-a-Bunch-Of-GPUs) and JBOA (Just-a-Bunch-Of-Accelerators) processing configurations and offers industry’s lowest latency and power while saving board space for customers by enabling usage models with a single-chip instead of multiple chips needed from competitors.
Connectivity has become the key barrier in supporting the memory bandwidth and processing speeds of data-intensive workloads such as AI/ML and genomics processing. With Apollo, XConn is breaking the bandwidth barrier by nearly doubling switch lanes delivered by competitive solutions and cutting port-to-port latency and power consumption per port by half.
“XConn is actively working in the expanding ecosystem that is accelerating CXL adoption,” said Jim Pappas, Director of Technology Initiatives, Intel. “By bridging the design gap between PCIe and CXL, advanced interconnect technologies, such as those being developed by XConn Technologies, are progressing the industry as CXL becomes the preferred standard for AI and HPC applications.”
“CXL 2.0 is the preeminent emerging technology to enable scalable memory capacity well beyond what traditional direct attached technologies support,” said Steve Pawlowski, corporate vice president of Advanced Memory Systems at Micron. “XConn’s innovative low latency CXL switch supports the creation of large, sharable memory pools across multiple servers to meet the growing demands of AI and HPC workloads. Micron is excited to continue collaborating with XConn to deliver advanced CXL solutions that will further propel the CXL ecosystem forward.”
The Apollo switch has been developed by a team of interconnect veterans that founded XConn in 2020. With decades of experience in the data center interconnect and switching field, the XConn leadership team also consists of actively contributing members of the CXL Consortium, Open Compute Project and PCI-SIG.