A guided tour across the NVM technology landscape – An interview with imec

The number of non-volatile memory (NVM) technologies in development at industrial and academic laboratories worldwide keeps proliferating every year and finding the right direction across the vast and diverse NVM technology landscape is no longer an easy task. An expert guide is needed, and Yole Développement (Yole) has one to propose to its i-MicroNews readers.

imec is a leading semiconductor R&D institution and has carried out extensive research with many leading industrial companies on a wide range of memory technologies, among which MRAM, ReRAM, IGZO-based DRAM, ferroelectric devices, and several others. Thanks to its globally acknowledged R&D work in semiconductor memory, imec is well positioned to understand and analyse the NVM technology landscape and assess its evolution.

Yole memory analyst, and author of the “Emerging Non-Volatile Memory 2021” report, Simone Bertolazzi talked with Gouri Sankar (memory program director at imec) about NVM technologies, trends, opportunities, and challenges in the field of emerging memory. Discover the details of their discussion below.

Gouri Sankar Kar (GSK): My name is Gouri Sankar Kar, I joined imec (Leuven, Belgium) in 2009 where I am currently working as memory program director. Before joining imec, I have worked at Infineon/Qimonda and at the Max Planck Institute for Solid State Research in Stuttgart, Germany. My first role at imec was to develop 3D NAND devices at the time when the industry was planning to move from 2D- to 3D-NAND architectures. After a few years, I started working on emerging memory with a focus on the ReRAM device family, and later I started the MRAM activity. Today, I am leading the Active Memory program at imec. In my role, I define the strategy and vision for research in 3D Storage Class Memory (3D-SCM), DRAM, FeRAM and MRAM for both stand-alone and embedded applications.

GSK: At imec, we have been investigating memory technology from the ReRAM family for more than 10 years. This is a broad class of memory technologies that include among other filamentary OxRAM, interface switching OxRAM, as well as conductive bridging RAM (CBRAM). The second group is magnetic memory, which historically evolved from field-driven switching (Toggle) to Spin Transfer Torque (STT), and today we are exploring several different flavours of such magnetic devices, such as Spin Orbit Torque (SOT), Voltage Controlled Magnetization Anisotropy (VCMA) and Voltage-Gate Assisted Spin-Orbit Torque (VGSOT). The third group is phase change memory (PCM) where we see a promising new variant which is called Interfacial PCM (IPCM). In conventional bulk PCM, the phase transition between amorphous and crystalline phases occurs across the volume of the active material, GST (GeSbTe) for example – but in IPCM other mechanisms can be involved. For instance, one theory ascribes the resistance change in IPCM to the change in position of germanium atoms. Then the fourth group is the ferroelectric memory with its different architectures, such as FeRAM, FeFET, and Ferroelectric Tunnel Junctions (FTJ). In the framework of the four memory groups, imec is working on different new material systems, including the emerging class of 2D materials, oxide semiconductors, topological insulators etc. which can be utilized for ReRAM, MRAM, PCM, DRAM as well as Ferroelectric memories.

GSK: At this stage, we do not focus on 3D XPoint structures (stacked 2D). When it was first introduced, 3D XPoint targeted cost efficiency, high performance, and low power application. However, cost-wise, manufacturing 3D XPoint involves several complex and expensive patterning steps. Moreover, in terms of performance/power, it has not been possible to reduce latency below 100ns and the switching-current density remains of the order of 20 MA/cm². All these aspects are not encouraging.

At imec, we are working on PCM technologies, but we are looking at different contours. We are also focusing on 3D vertical architectures with the aim of reducing cost per bit, exploring a variety of atomic layer deposition (ALD) approaches and related materials.

GSK: Besides the NVM technology itself, there are certainly other challenges. For instance, Intel Optane products based on 3D XPoint have two different interface variants: PCIe and DIMM. For PCIe, the cost competition is much higher as you are close to the SCM-storage level, and there is strong cost pressure set by competing NAND-based technologies (e.g., Z-NAND, XL-NAND).

Intel will likely maintain the Optane DIMM portfolio building a complete ecosystem around it. They have that capability to do that because they hold the full architecture of the CPU processor and its memory interface. In the future, I see CXL (Compute Express Link) as a very promising interface for emerging memory. CXL will be filling the PCIe-DIMM gap enabling new possibilities for market adoption of new SCM technologies. 

GSK: In my opinion, we should not dream about a universal memory, it does not exist because no single technology can fulfil all the requirements for so many different applications. Today, the evolution of information technology (IT) systems and the rise of new paradigms in computing are opening new possibilities for emerging memory. The core work consists in finding the right memory technology for the right computational system, as we have now many more avenues to follow. Most of the emerging memory technologies (for example, RRAM, PCRAM, MRAM FeFET, FeRAM, FTJ etc.) are now being investigated in the context of machine learning (ML), but I think we should be more careful. We should first look for the technology requirement of the ML application and then try to fulfil that requirement with the right technology. Instead, bringing all the new memories in the context of machine learning risks to be a waste of time and resources.

GSK: I think the breakthrough needs to come from the memory-switching mechanism, which has not evolved significantly over the last decades. All the switching mechanisms in use today, including ReRAM, PCRAM, ferroelectric and magnetic switching, exist for several decades. In this area, improvements are needed, or new switching mechanisms must be introduced.

Today, lot of research work is carried out on new material systems to improve device performance, energy efficiency or shrink cell size. At the same way, different device architectures are being developed, such as SOT, VGSOT and VCMA. All these structures can bring significant advantages and solve many problems, but they also requirenewmaterials. For instance, it is not possible to develop a good VGSOT device without a suitable SOT track layer; it is also important to have a material with a very good VCMA coefficient. Hence, the material search remains the key part.

GSK: Embedded STT-MRAM has already achieved market maturity, and we see some products coming out, such as Huawei’s smartwatches based on Sony’s GPS chips. These are manufactured by Samsung with 28nm eMRAM. In the future, other players could target last-level cache applications in processors. Of course, there is a gap between the advanced logic nodes and this technology, but we will definitely see progress in this area. Once introduced, STT-MRAM will remain for at least a few generations before the industry will attempt to replace it.

Voltage control magnetization anisotropy (VCMA) – holds promise because of its low-power consumption, high performance, and good scalability, but of course, we need a huge breakthrough in the material research.

At imec we are currently working on the voltage-gated SOT device, we call it VGSOT. We have published multiple papers on the SOT domain. Today, the biggest challenge for SOT is the bit-cell size, which is too large, it is almost comparable to that of SRAM.  Instead, the VGSOT device has a promising bit-cell size: we see it can get close to the STT-MRAM bit-cell size while outperforming STT-MRAM in terms of performance and energy consumption.

We are recently considering one more MRAM technology: domain wall memory (DWM). If one day some part of the logic is going with the STMG (i.e., spin torque majority gate), then you need a common platform where the logic and the memory can come close together. And the domain wall memory can play a big role there: on the same magnetic bars, you can connect the logic and the memory at the same time.

GSK: We see three different categories of ferroelectric devices: ferroelectric RAM (FeRAM), ferroelectric FET (FeFET), and Ferroelectric Tunnel Junction (FTJ. FeRAM is the most mature and the world’s oldest ferroelectric memory. New material systems from the perovskite family or from the wurtzite family are enabling a high remnant polarization (P_r) value exceeding ~150 µC?cm^-2. However, thickness scaling as well as voltage scaling remain challenging for FeRAM. These materials are paving the way towards 2D FeRAM based on very small dot-like capacitor (50-60nm or even smaller). Of course, patterning is the key challenge in this context because if the nanostructures get damaged, then the ferroelectric properties get lost.

FeFETs and FTJs are newly emerging ferroelectric devices and are very promising. At IEDM 2020, Intel presented a channel last approach for FeFET that I believe has good potential. The advantage arises from decoupling the front end and back end, so that memory manufacturing can be carried out entirely in the back end. This is definitely a very interesting route to follow in the future for both eFlash replacement, as well as working memory (e-DRAM-like).

GSK: Indeed, integration in CMOS process flows is a key point, and often academic researchers are not fully aware of that. OxRAM is the less challenging, as its switching materials are simple metal oxides, and the semiconductor industry has been using them for relatively long time, for instance as high-? gate oxides in logic devices. Material-wise, MRAM is more complex: the thermal budget for processing magnetic layers must be compatible with the overall manufacturing flow; moreover, protecting the MTJ stack from moisture can be a hurdle. Now, if we look at ferroelectrics, the biggest challenge consists in scaling the active-layer thickness while preserving optimal critical field (E_c) and high remanent polarization (P_r). For ferroelectrics, patterning can be also complex as the etching rate depends on the crystal structures of the ferroelectric material. Finally, the presence of hydrogen in the CMOS environment – particularly during the back end of line (BEOL) – could have a detrimental impact on the ferroelectric material properties.

Hydrogen/oxygen contamination and thermal-budget constraints are hurdles also in the case of indium-gallium-zinc-oxide (IGZO), a material system that has been recently investigated by imec for DRAM applications.

For imec, it is very important that the test vehicles are CMOS compatible. They are based on processes that are used for the CMOS front end of line (FEOL) or BEOL manufacturing.

GSK: First, we evaluate internally the technology roadmaps. Imec has its own roadmap that does not necessarily correspond to the semiconductor industry’s roadmap. We try to predict in which direction the industry is moving and what their needs will be for N+3, N+4, N+5 technology nodes (note: N is the current technology node), even 10 years and beyond from now. Also, we try to see from a system-level perspective in which direction computing is moving, and what will be the corresponding hardware requirements. And based on that, we define some device-level specifications through discussions with our system engineers, detailed design-technology co-optimization (DTCO) studies, internal brainstorming, deep literature study, etc. The goal is to down select the technologies that have the highest potential to start working on them in a small lab-scale or a small device-scale learning platform. In parallel, such works triggers new computational studies – e.g., ab initio simulations – to find a new material system that fulfils the requirements and improves the device performance further. If we see that all aspects are progressing in the right direction, then we start working with tool vendors to bring the new platform to industrial manufacturers. We collaborate with almost all the tool suppliers for developing new material systems with state-of-the-art tools and qualify them through a set of physical and electrical characterisation approaches.

For developing a new memory technology, we typically start from the single-cell device level and we study the performance, the reliability, and several other figures of merit. Once we see that the technology has strong potential, then we move to a megabit-array layout to acquire more confidence through large-data statistics, and after validation we start making full megabit arrays. To that purpose, the test chip with the full megabit arrays. The wafer with the FEOL (including logic circuitry) is then taped out by our foundry partner and we integrate the BEOL with all the memory elements.

Often, some bilateral projects open for us. If you have the right test vehicle, the right tools for developing the right material system, and the right technical and scientific expertise, then you can start bilateral collaboration projects with e.g. start-up companies. They might have different IP ideas, but they may not be able to implement them in a real fab environment. And that’s where imec is playing today a very crucial role.

GSK: I can give you a very good example related to resistive RAM technologies. It takes almost seven-to-eight years, from a laboratory device (proof-of-concept) to a large megabit array.

I would like to stress that foundries or IDMs are not willing to adopt a new technology if that does not show a real potential for disruption. It is not enough to demonstrate a factor of 2-3 better performance or smaller cell size compared to existing technologies. The improvement should be measured in orders of magnitude! And marketwise, there is need for a killer application. The clear example is 3D XPoint: it is a very good memory, but still lacking a killer application, so it is struggling to take off.

GSK: Imec did an extraordinary work during the pandemic, keeping all operations 100% running. In 2020 we processed more wafers than in 2019. It is a paradox, but we could say that the less people in the fab, the better it is for the performance of the fab. Today, the employees who do not need to go to the fab, are working 100% from home, while those that need to access the fab can do it at any time, but they have very strict rules. And most of the electrical characterisation protocols can be run from home or with a limited direct interaction.

In terms of operations and delivering results to partners, we are really satisfied. But of course, the downside is that now people must do more work. There are a lot of small things you can solve just by talking to each other at the coffee corner or at the stairs, in the hallway… but now for everything, you have to make a call, you have to arrange a meeting, to have a discussion. Face-to-face communication with eye contact is very important because you can bring the right message to people and people can get the right message from you. With remote interactions, misunderstanding can happen, and more time has to be spent in solving problems.

Thank you, Gouri Sankar Kar, for sharing imec’s view on emerging memory with our IMN readers. It was really a pleasure to discuss and learn from you about imec’s work focusing on such a wide spectrum of different technologies.

Interviewee:

Gouri Sankar Kar received the PhD degree in semiconductor device physics from the Indian Institute of Technology, Khragput, India in 2002. From 2002 to 2005, he was a visiting scientist at Max Planck Institute for Solid State Research, Stuttgart, Germany, where he worked with Nobel Laureate (1985, Quantum Hall Effect) Prof. Klaus von Klitzing on quantum dot FET. In 2006, he joined Infineon/Qimonda in Dresden, Germany as lead integration engineer. There he worked on the vertical transistor for DRAM application. In 2009, he joined imec, Leuven, Belgium, where he is currently program director. In this role, he defines the research strategy and vision for SCM, DRAM, FeRAM and MRAM programs both for stand-alone and embedded applications. He has authored, co-authored more than 200 peer-reviewed publications, many articles and holds patents in the memory domain.

Interviewer:

Simone Bertolazzi, PhD is a Senior Technology & Market analyst, Memory, at Yole Développement (Yole), working with the Semiconductor, Memory & Computing division. As member of the Yole’s memory team, he contributes on a day-to-day basis to the analysis of nonvolatile memory markets and technologies, their related materials and fabrication processes.
Previously, Simone carried out experimental research in the field of nanoscience and nanotechnology, focusing on emerging semiconducting materials and their opto-electronic device applications. He (co-) authored several papers in high-impact scientific journals and was awarded the prestigious Marie Curie Intra-European Fellowship.
Simone obtained a PhD in physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland), where he developed novel flash memory cells based on heterostructures of two-dimensional materials and high-? dielectrics. Simone earned a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude

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