The latest progression of Fan-Out packaging – Interview of Samsung Electronics

Expanding at a 15.9% Compound Annual Growth Rate (CAGR), Fan-Out Packaging will be worth $3,046M by 2025, up from $1,256M in 2019, as reported in Yole Développement’s Fan-Out Packaging: Technologies and Market Trends report, 2020 edition.

2019-2025 Fan-Out packaging revenue forecast per market class

The underlying new drivers for Fan-Out Packaging are 5G wireless networking and High Performance Computing (HPC) applications. Big data technology can only be enabled by 5G and beyond. Wide bandwidth needs higher frequency millimeter wave (mmWave) solutions. The purpose of Antennae-in-Packages (AiPs) is to reduce signal loss with shorter interconnect lines. And Fan-Out Packaging is a validated solution to enable low transmission loss and high antenna performance. Also, industry players are splitting System on Chip (SoC) dies into multiple smaller separate chips with different functions, where each function can be built with an optimized node and cost. Hence, Fan-Out Packaging is being adopted as one of the key advanced packaging platforms to integrate these chips by reconstituting the chips back into one package. In 2018, Samsung Electro Mechanics (SEMCO) made a significant impact in Fan-Out Packaging market space by adopting High Density Fan-Out Panel Level Packaging (HD FOPLP) in its smartwatch. By acquiring SEMCO’s FOPLP business in 2019, Samsung Electronics is stepping up the synergy between semiconductor manufacturing and packaging. Hence, we are glad to interview Seung Wook Yoon from Samsung Electronics on his viewpoints on Fan-Out Packaging.

Favier Shoo (FS): After acquiring Samsung Electro Mechanics (SEMCO)’s PLP business in 2019, Samsung Electronics is sending a strong signal about its intention and willingness to invest in semiconductor Fan-Out Packaging technology. Could you introduce Samsung Eletronics’s Fan-Out Packaging activities?
Seung Wook Yoon (SWY): As officially announced in 2018, Samsung is now engaged in high volume manufacturing of low profile thin FOPLP, which is widely used for consumer and wearable products. We are also working to expand its use in mobile products

FS: In 2020, COVID-19 has caused contraction of economic activity. Fan-Out Packaging revenue is expected to drop from $1,256M in 2019 to $1,237 in 2020. However, Fan-Out Packaging revenue is expected to experience a strong recovery in 2021, achieving $1,840M. Yole Développement does not expect impact of COVID-19 crisis to last forever and ironically may even catalyze and accelerate digital transformation? What is your view on this?
For advanced packaging such as fan-out wafer level packaging (FOWLP) and FOPLP, there is high demand for new features in assembly and packaging for its advantages of form factor, performance and access to 2.5 and 3D solutions, so it will continue developing and expanding its applications.

FS: Ultra High Density Fan Out (UHD FO) has more than 18 inputs and outputs (I/O) per square millimetre and line and spacing (L/S) measurements in the redistribution layer (RDL) of 5µm and 5µm. It can be viewed as an upgrade from High Density (HD) FO where the L/S suits a larger package size for HPC applications like networking and data center servers. In 2020, Yole clearly defined FO packaging market classes into UHD FO, HD FO and Core FO based on I/O densities and L/S. More UHD FO packaging will be needed as cost-effective high-end packaging as compared to 2.5D interposers. Would you agree that HPC-driven products will be a new killer application for UHD FO?
SWY: I fully agree with your points. UHD FO would be unique and beneficial for low/mid-end 2.5D applications with cost-effective solutions such as server network or HPC compared to 2.5D silicon Through Silicon Via (TSV) interposer packaging.

YS: Fan-Out Packaging is going to experience one of the sharpest growths for AiP applications, driven by 5G-driven, at a whopping 76% CAGR from 2020-2025. Separately, various processor ((x)PU) die partitioning and (x)PU and High Bandwidth Memory (HBM) applications are also growing strongly, with a 20% CAGR from 2019-2025 and 52% CAGR from 2021-2025 respectively, with a need for higher computing performance. Would you agree with these market drivers and trends for Fan-Out Packaging revenue?
: Currently available FOWLP AiPs are mainly for Advanced Driver Assistance System (ADAS) applications. For 28 GHz or 39 GHz substrate-based packages or modules, this would be good to cover its 5G performance. But above 60 GHz, it would be necessary to use FOWLP/FOPLP or WLP with RDL.
The chiplet device market would have high growth potential, enabling Logic+Logic, or Logic+Memory or Logic+Radio Frequency (RF)/Analog or Power Management Integrated Circuits (PMICs) or multiple devices in highly integrated, heterogeneous integration.

FS: Fan-Out packaging technology is not only a bridge to chip-package interaction (CPI) mismatch in pitch size, but it is also a viable solution for heterogeneous integration of functionalities in a desired package dimension and design. Moving forward, what do you think are the technical requirements for Fan-Out packaging?
: For further highly integrated solution, like heterogeneous integration with chiplet packages, it needs finer line width and spacing and multiple-layer RDL technology with proven assembly yield and robust reliability. In addition, a shorter assembly cycle time would also be required.

FS: Fan-Out packaging’s key benefit is its ability to integrate dies together flexibly, in thinner packages. It can displace 2.5D interposers with fine L/S Fan-Out packaging on substrates, as well as flip-chip and advanced substrates. Will Fan-Out packaging continue to cannibalize and phase out other packaging technologies?
: Wire bonding is still in high volume production, and even flip chip is being well used in recent decades for mobile or high-end applications. We know that every package type has a unique position, for cost, reliability, design flexibility, supply chain or performance for many different reasons. But we saw that only a few representative package structures survive in Chip Scale Packaging (CSP) and Wafer Level CSP (WLCSP), due to cost effectiveness, manufacturing-friendliness and robust reliability. It would be the same for FO packaging. It should have good positions in several mobile and automotive applications in the last ten years.


Dr. Yoon is currently working as Corporate VP/Head of Team of Package Technology Planning, Test & System Package, Samsung Electronics. Prior to joining Samsung, He was director of group technology strategy, STATS ChipPAC, JCET Group. He also worked deputy lab director of MMC (Microsystem, Module and Components) lab, IME (Institute of Microelectronics), A*STAR, Singapore. ”YOON” received Ph.D degree in Materials Science and Engineering from KAIST, Korea. He also holds MBA degree from Nanyang Business School, Singapore. He has over 300 journal papers, conference papers and trade journal papers, and over 20 US patents on microelectronic materials and electronic packaging.


Favier Shoo is a Technology and Market Analyst in the Semiconductor & Software division at Yole Développement, part of Yole Group of Companies. Based in Singapore, Favier is engaged in the development of technology & market reports as well as the production of custom consulting reports.
During 7 years at Applied Materials as a Customer-Application-Technologist in the advanced packaging marketspace, Favier developed a deep understanding of the supply chain and core business values. As an acknowledged expert in this field, Favier has provided training and held numerous technical review sessions with industry players. In addition, he has obtained 2 patents.
Prior to that, Favier worked at REC Solar as a Manufacturing Engineer to maximize production capacity.
Favier holds a Bachelor in Materials Engineering (Hons) and a Minor in Entrepreneurship from Nanyang Technological University (NTU) (Singapore). Favier was also the co-founder of a startup company where he formulated business goals, revenue models and marketing plans.

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