High-end performance packaging: breaking performance barriers?

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The current AI/HPC demand has brought high-end performance packaging to the spotlight.


  • The high-end packaging market is projected to exceed US$28 billion by 2029, with a CAGR 23-29 of 37%.
  • TSMC and other top foundries, big IDMs like Intel and top memory providers YMTC, Samsung, SK Hynix, Micron and leading OSATs – ASE, SPIL, JCET, Amkor are all vying for a share of the high-end packaging market.
  • The primary technological trend across all high-end performance packaging platforms, regardless of type, is the reduction of interconnection pitch.

Breaking the high-end packaging market down by end markets, the largest segment is telecom & infrastructure, which accounted for over 67% of the revenue in 2023. Close behind is the mobile & consumer market, the fastest-growing segment with a 50% CAGR23-29. This significant growth is driven by increasing demand and higher ASPs for high-end packages compared to less advanced packages, as value shifts from the front-end to the back-end due to 2.5D and 3D platforms.

Stefan Chitoraga Technology & Market Analyst, Semiconductor Packaging at Yole Group
3D stack memory technologies—including HBM[3], 3DS[4], 3D NAND, and CBA DRAM[5]—are the most substantial contributors, expected to represent more than 70% of the market by 2029. The fastest-growing platforms include CBA[6] DRAM, 3D SoC[7], Active Si[8] Interposer, 3D NAND stack, and embedded Si bridge.

In its new annual High-end Performance Packaging 2024 report, Yole Group analyzes key market drivers, benefits, and challenges associated with high-end performance packaging by application. Furthermore, the report describes the various existing technologies, their trends, and roadmaps, while considering the supply chain and the broader landscape of high-end performance packaging. Additionally, it updates the business status of high-end performance packaging markets and provides market forecasts for the coming years, estimating future trends.

Titre du visuel

june 2021

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Thematic(s) :

Vishal Saroha Technology & Market Analyst, Semiconductor Equipment at Yole Group
The primary technological trend for all high-end performance packaging platforms is reducing interconnection pitch, involving TSV s, TMV s, microbumps, and hybrid bonding. Additionally, via diameter and wafer thickness are decreasing, which is essential for integrating complex monolithic dies and chiplets, supporting faster data processing, lower power consumption, and higher density integration.

One significant development is 3D SoC hybrid bonding, a key technology for next-generation advanced packaging. It enables smaller interconnection pitches and larger SoC surfaces, facilitating the stacking of chiplets from partitioned SoC dies and allowing for heterogeneous integration. TSMC is at the forefront of 3D SoIC packaging using hybrid bonding, followed by Intel with its Foveros Direct and Samsung with its X-Cube. Furthermore, collective die-to-wafer hybrid bonding is expected to commence with HBM4E and a 16-high DRAM stack.

Driving the adoption of high-end performance packaging is the trend toward chiplet and heterogeneous integration. Products like Intel’s Sapphire Rapids (EMIB), Ponte Vecchio (Co-EMIB), and Meteor Lake (Foveros) are prime examples of this approach. Amazon and AMD also employ this technology, with Nvidia adopting it for the Blackwell series. More packages with partitioned or duplicated dies are anticipated soon, including high-end ADAS applications.

The general trend is to combine 2.5D and 3D platforms within the same package, a concept some in the industry refer to as 3.5D packaging. As a result, future packages will integrate chiplets using 3D SoC, 2.5D interposers, embedded silicon bridges, and co-packaged optics. This evolution will further complicate high-end performance packaging, making it even more sophisticated and efficient.

Yole Group’s semiconductor packaging team invites you to follow the technologies, related devices, applications, and markets on

In this regard, do not miss Gabriela Pereira, Technology & Market Analyst, Semiconductor Packaging’s presentation, Fan-out Packaging Reaching New Heights: Market and Technology Overview at the IEEE ELECTRONICS SYSTEM-INTEGRATION TECHNOLOGY CONFERENCE – ESTC 2024 in Berlin, Germany, from September 11 to 13.

Interested in an on-site meeting with us? Send a request to

Stay tuned!


  • CAGR : Compound Annual Growth Rate
  • ASP : Average Selling Prices
  • HBM : High Bandwidth Memory
  • 3DS : 3D Stack (DRAM)
  • DRAM : Dynamic Random Access Memory
  • CBA : CMOS Bond Array
  • SoC : System-on-Chip
  • Si : Silicon
  • TSV : Though-Silicon Via
  • TMV : Through-Mold Via

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