System-in-Package industry: IDMs, OSATs, and foundries are taking the advantage

Through enabling design and supply chain agility, SiP will reach more than $19B by 2026.

“SiP has become synonymous with technologies ranging from high-end die-to-die chiplet-type advanced integration to devices found in mobile handsets with increased integration and functionality leveraging best-in-class advanced packaging processes.” asserts Vaibhav Trivedi, Senior Technology & Market analyst, Packaging, within the Semiconductor, Memory & Computing division at Yole Intelligence, part of Yole Group. He adds:“The SiP platform is crucial in achieving ‘More than Moore’ in the race for heterogeneous integration, where advanced packaging remains at the forefront with front-end technology.”

The SiP market is expected to increase from US$14 billion in 2020 to US$19 billion+ in 2026. The SiP product line includes high- to mid-end SiP devices, such as computing and data center applications, with much higher margins than the low-end SiP devices found in mobile handsets. High-end SiP market segment is expected to grow at a 9% CAGR between 2020 and 2026, whereas the low-end RF SiP one, found in mobile phones, is expected to grow at a slightly lower CAGR of 5% from 2020 to 2026.

In this dynamic context, Yole SystemPlus, part of Yole Group of Companies, investigates disruptive semiconductor technologies and related markets in depth. They point out the latest innovations in the packaging industry and underline the business opportunities.
Released today, the System-in-Package Technology and Market Trends 2021 report from Yole describes technologies that can be classified as “System-in-Package”, identifies and details the SiP platform’s key process steps. Including market trends and forecasts, supply chain, technology trends, technical insights and analysis, take away and outlook, this study also delivers an in-depth understanding of the ecosystem and main players’ strategies.
In addition, the Smartphone Design Win Quarterly Monitor from the reverse engineering and costing company, Yole SystemPlus, utilizes data from representative phones (65+ phones per year torn down in the Yole SystemPlus Phone Teardown Track Module) and follows the OEM market share. The monitor provides the detailed design wins and related supply chain for the eight phones being analyzed, along with supply chain alternatives for the main devices. It also delivers added value analysis of the packaging technologies selected by the leading smartphone manufacturers and their suppliers.

Yole SystemPlus presents today their vision of the SiP technologies and related markets.

In the new System-in-Package Technology and Market Trends 2021 report, SiP solutions are differentiated into three categories:
• The dominant flip chip/wire bond-based packaging form factors
• FO based multi-die form factors
• And the ED form factors.
The SiP remains a crucial platform as it allows the OEM customer to integrate one or more functionalities onto a substrate-based package instead of integrating it as a discreet component on the PCB . The compact and miniaturized package is ideal for mobile handset devices. SiP provides flexibility and freedom to the designers in terms of sourcing the die and passive components for best-in-class cost and performance benefits. With the rise in SiP devices, many device wafers have adopted flip chip bumping or ball drop processes as these can be easily attached in SiP Packages, instead of using a wire bonding process to attach a die. WLCSP components have risen mainly due to the SiP platform’s capability to integrate such varied form factors in a single package.
According to Favier Shoo, Team Lead Analyst, Packaging, within Semiconductor, Memory and Computing Division at Yole: “In terms of technology and a roadmap, the SiP platform continues to push the boundary in the race to produce denser, thinner, and smaller form factors. These new process technologies include double-side molding technologies that eliminate the underfill operation from the bottom die resulting in an improved cost structure and manufacturing efficiencies”.
In addition to dual side molding, compartmental and conformal shielding remains another key process technology for RF-SiP devices. In terms of package height, OSATs are expected to push for 0.6 mm total package height for SiP devices in the coming years. With the deployment of 5G, increased development of materials is seen, to improve the reliability of SiP devices, especially in molding and solder ball materials.
Favier Shoo adds: “We can expect the industry to push the boundary of chip shooter tools to enhance the accuracy of component placing and throughput. In addition, we can also expect novel, reliable packaging materials to set the stage for the next set of SiP devices to drive heterogeneous integration further”.

SiP global business models have evolved significantly over the past five years. OSATs have dominated in the past, and the demand was somewhat scattered in the SiP landscape 5-8 years ago. However, with mobile handsets, RF evolution, and 5G deployment, SiP has come of age and can robustly support multiple markets, starting with the low-end RF SiP markets dominated by top OSATs and driven by leading OEMs, such as Apple and Samsung.
In this regard, Yole SystemPlus made a special focus dedicated to the RF technologies and SiP solutions in its Smartphone Design Win Quarterly Monitor Q1 2021. Yole SystemPlus’s analysis offers a clear view of the market leading semiconductor companies and a direct comparison between OEMs.
The high-end SiPs remain on a higher growth trajectory with post-pandemic demand accelerating infrastructure spend globally. This explosion in multiple segments has prompted IDMs, foundries, EMS houses, and OSATs to compete in this thriving market. ASE’s USI generates a significant portion of ASE’s revenue and will approach 50% of the revenue in a few years.
OSATs are developing capabilities to mount anywhere from 50-100 passive SMT components and manage a supply chain that was foreign to them just a few years ago.
IDMs, such as Intel and Samsung, are driving hybrid die-to-die interconnect-stacked-packaging, such as Intel’s Foveros architecture and Samsung’s x-cube architecture. These die-to-wafer or die-to-die interconnects will gravitate towards hybrid bonding, improving device performance and bandwidth in a near future. Intel is also targeting a Co-EMIB server product on 7 nm node by 2023.