Technology, Process and Cost

Micron’s 176-layer 3D NAND Memory

By Yole SystemPlus — Mar 2022

Micron’s triple-level cell 3D NAND with 176 active wordlines using replacement-gate technology to enhance performance.

Micron Technology’s revenue increased by 29% between fiscal years 2020 and 2021, with revenue reaching $27.7B in FY 2021. The NAND memory business contributed 25% to the total revenue. In Q2 2021, Micron introduced its 176-layer triple-level cell NAND, which targets a broad range of applications including automotive, mobile, client, consumer, and datacenter. It boasts the highest wordline count of any commercial NAND memory product in the world.

Micron transitioned from floating-gate to 3D NAND replacement-gate technology as a solution to overcome capacity limitations, increase power efficiency, and improve read-and-write speeds. The replacement-gate technology used in Micron’s 176-layer has a nonconductive layer of silicon nitride which is used as a NAND storage to trap and store charges. Moreover, a metal control gate is used in Micron’s 128-layer and 176-layer instead of polysilicon floating gate. This modifies Micron’s manufacturing process compared to the previous floating-gate technology process. Micron’s 3D NAND memory uses CMOS under-array technology, and the 3D NAND flash memory layers are built on the CMOS transistors. This allows more than 90% of the die area to be used for the memory cell array, compared to building CMOS transistors on the periphery. CMOS under-array also significantly reduces the total die size, hence increasing the potential number of dies and total wafer capacity. To reduce the NAND array stack height, Micron reduced the wordline thickness and wordline pitch.

Micron also introduces a new manufacturing process to create the tungsten contacts on the staircase region. This report details this new technique, which involves creating staircase contacts by depositing and patterning a thin layer of tungsten material on the staircase wordline pads. This improves the contact between the wordlines and the tungsten staircase vertical contacts, and results in additional patterning steps in the manufacturing process. Our report also analyses Micron’s 512Gb TLC NAND die, which is Micron’s 2^nd-generation of charge trap flash that uses two decks to stack a total of 195-layer wordlines. The die density is increased by more than 30% compared to Micron’s previous 128-layer NAND.

This report includes an overview of the 1TB solid-state drive teardown to extract the NAND memory packages. The full physical analysis is accompanied by optical images and high-resolution SEM images of the package and die. The package substrate layers and the position of the dies in the package are revealed through cross-section images. The die analysis includes two cross-sections to reveal the CMOS transistors, the metal layers between the CMOS transistors, and the NAND array, as well as the wordline layers stacked in two decks and the cell memory storage material. The cross-section images also focus on the NAND memory structure and the charge trap layers. EDX analysis identifies the materials used in the 3D NAND manufacturing process. This report also details the manufacturing process of the 176-layer 3D NAND memory and the final package assembly. Lastly, a cost analysis provides an estimation of Micron’s 176-layer TLC, CuA NAND memory wafer cost, die cost, and component cost.