AMD 3D V-Cache with TSMC SoIC 3D Packaging

KEY FEATURES:

• Detailed photos
• Precise measurements
• Materials analysis
• Manufacturing process flow
• Supply chain evaluation
• Manufacturing cost analysis
• Industry’s first 3D V-Cache compute die bonded with cache memory
• System-on-Chip (SoC) with multiple dies and different foundries
• TSMC System on Integrated Chips (SoIC) technology
• Hybrid bonding technology
• High density Through Silicon Vias (TSVs)

• AMD
• TSMC
• GlobalFoundries

Overview / Introduction 

• Executive Summary
• Specifications
• Reverse Costing Methodology
• Glossary

Company Profile & Supply Chain 

• AMD Financials
• AMD Products
• AMD V-Cache
• Market Analysis

Teardown Analysis 

• Summary
• AMD Ryzen 7 Processor Package
• Package Assembly
  • Views & Dimensions, X-Ray Analysis
  • Cross Section
  • Opening
• I/O Die, CPU Die, Cache Die
  • Views & Dimensions
  • Delayering & Process
  • Die Cross Section 
• Structural Silicon die
  • Views & Dimensions
  • Cross Section

Manufacturing Process Flow 

• I/O Die Front End & Fab Unit
• CPU Die Front End & Fab Unit
• Cache Die Front End & Fab Unit
• Structural Silicon Die Front End & Fab Unit
• Carrier silicon (1 Cache & 2 structural die assembly)
• Hybrid bonding
• Final Test & Assembly

Cost Analysis 

• Cost Analysis Summary
• Yields & Explanations
• I/O Die Cost
• CPU Die Cost
• Cache Die Cost
• Structural Die Cost
• Hybrid bonding Cost
• Package Assembly
• Component Cost

Estimated Manufacturer Price Analysis 

• Estimation of the Manufacturer Price

Feedback

Related products 

About Yole Group  

We expect revenue from Central Processing Units (CPUs) to reach $70 billion in 2022. The server market comprises more than 36% of this. But AMD Ryzen 7 5800x is a gaming processor using AMD’s V-Cache with Static Random Access Memory (SRAM) cache dies stacked on top of a CPU die. It is a high-performance processor utilizing TSMC’s 3D System on Integrated Chip (SoIC) chip-on-wafer (CoW) stacking process and hybrid bonding technology.

AMD has adapted its System on Chip (SoC) design, optimizing the manufacturing cost of the component by partitioning the SoC into multiple chips. This involves scaling the most critical circuit blocks on the SoC and using a less advanced technology on blocks that that do not require an advanced technology node. The compute chip architecture is equipped with 8 CPU cores using advanced 7nm fin Field-Effect Transistor (FinFET) technology whilst the Input/Output (I/O) chip uses a less advanced technology node from GlobalFoundries. Separating the SoC into multiple dies allows flexibility in chip foundry choice and optimizes cost. AMD Ryzen 7 uses a 3D multichip integration, which is TSMC’s System on Integrated Chips (SoIC) technology, offering exceptional bonding pitch, scalability and high-power efficiency compared to conventional 3D integration using micro bumps.

Hybrid bonding connects the cache memory dies to the CPU compute die. The process involves direct copper-to-copper bonding. 3D V-Cache technology is a packaging technology using through silicon via (TSV) interconnections for higher data transfer rates between chips. It achieves reduced bond pad pitch, which is estimated to be less than 10µm, higher interconnection density, increased bandwidth, and ultra-robust interface between the two dies. AMD claims that hybrid bonding offers 15 times higher interconnect density and higher energy efficiency accompanied by superior thermal conductance compared to micro bump 3D solutions.

This full reverse costing study was conducted to provide insights into the technology data, manufacturing cost, and selling price of the AMD Ryzen 7 5800x. To reveal all the details of the AMD Ryzen 7, this report includes a front-end construction analysis to reveal the most interesting features of the integrated chips, their process, as well as package assembly. The report focuses on the hybrid bonding used to connect the cache die to the CPU die. In addition, a complete construction analysis is done using Scanning Electron Microscope (SEM) cross-sections, material analyses, and die delayering. 3D X-ray Computed Tomography (CT) scans reveal the layout structure of the whole chip package. Lastly, this report contains a complete supply chain, cost analysis and a selling price estimation of the AMD 7 processor.