Apple - APU - Co-Processor R1 - From Apple Vision Pro

Key Features

• Detailed photos​
• Precise measurements​ on package and SoC die analysis
• Packaging materials analysis​
• Physical analysis on LLW DRAM planar and cross-section
• SoC die floorplan​
• Package/die/floorplan comparison with the predecessor
• Manufacturing process flow
• Supply chain evaluation​
• Manufacturing cost analysis

What's new?

• The first consumer chips that integrates LLW DRAM to enhance the latency for AR/VR headset
• New IP design with the unconventional  “Eye processors” for the real-time sensor/camera signal processing

Product objectives

• Provide detailed technology data, manufacturing cost and selling price.​
• Teardown details on Apple Vision Pro to reveal the configuration and components around the main processor Apple M2 and the coprocessor ​R1 SoC.
• Physical analysis of TSMC InFO-R packaging, SK hynix LLW DRAM and processor die with EDX, optical microscope and scanning electron scope.​
• Understand the technology for advanced computing product and its supply chain.
• Provide the information regarding the SoC package size, die size and die delayering photo to know the chip manufacturing ​
• Understand the new IP architecture from detailed floorplan analysis.​
• Have a clear view on the supply chain and cost structures of the Apple R1 chip.

A co-processor paired with Apple M2 that boosts the XR computing in Apple Vision Pro

Apple's R1 System-on-Chip (SoC) is the first Apple silicon dedicating to AR/VR and mixed-reality (categorized broadly as XR) computing. Co-processing with M2 SoC and used with Apple’s self-design visionOS operating system, this cutting-edge chip powers the Apple Vision Pro which makes a great jump forward the XR experiencing.

R1 SoC features TSMC InFO-R packaging techniques, a TSMC 5 nm processor die design, low latency wide IO (LLW) dynamic random access memory (DRAM) and integrated passive devices (IPD) on the backside of the chip. All of these collectively optimize the efficiency in real-time processing and push the boundaries of what is possible in headset electronics. In this report, a complete analysis on the physical structure from packaging, DRAM die and processor is presented. With a meticulous examination of the planar view and cross-section through high-resolution images taken by using the optical microscope and scanning electron microscopy (SEM), the report offers a great visual guide to understand the modern computing technology.

The detailed analysis also delves into the core of the processor die, uncovering Apple’s innovative design. The in-depth floorplan reveals the distinct configuration and provides a view on the critical Eye Processor (managing the display and camera), LLW DRAM interface (realizing high-band width communication between processor and memory) and several types of function blocks. A precise measurement on each computing core area is also included to understand how Apple enhances the performance and reliability of the R1 SoC.

Beyond the technical study, this report extends the analysis to an economic aspects of the R1 SoC. To perceive the crucial dynamics of semiconductor industry for strategic planning and competitive benchmarking, the report furnishes with a detailed cost analysis, breaking down the manufacturing and supply chain.

Overview / Introduction

• Executive Summary
• Product Specification
• Reverse Costing Methodology
• Glossary

Company Profile

• Company Profile
• Apple Products
• Market Analysis

Physical Analysis

• Summary
• Smartphone Dismantle
• Package Analysis
• DRAM Analysis (Dimensions & Opening)
• SoC Die
• Floorplan

Manufacturing Process Flow Analysis

• Global View
• Die Process
• Fab unit
• Assembly Process
• Final Test

Cost Analysis

• Summary & Supply Chain
• Yields Explanation & Hypotheses
• Front-End Wafer Cost
• Die Cost
• Packaging Cost
• Component Cost

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About Yole Group

• Apple
• TSMC
• SK Hynix