Technology, Process and Cost

Apple’s A14 Bionic System-on-Chip

By Yole SystemPlus — Nov 2021

Analysis of Apple’s A14 SoC in the iPhone 12 and iPad Air 4th, including TSMC’s first 5nm processor with updated inFO packaging.

Apple’s A14 Bionic arrived on the scene in 2020 right as the smartphone processor industry was building up to a revenue of $29.7b for the year. Apple’s SoCs have consistently been at the leading edge of performance and process technology, and the A14 is no exception.
This full reverse costing study was conducted to provide insight on the technology data, manufacturing cost, and selling price of the Apple A14 Bionic System-on-Chip (SoC).
Apple has always developed its own processors for commercial products. Among its entire processor series, the A series has contributed most to Apple’s net sales. This is because Apple’s iPhone is powered by an A series chip. Moreover, the A series is also applied in many other hot products such as the iPad, iPod, and Apple TV. Today the newest generation, A14 Bionic, is potently supporting the iPhone 12 Pro and iPad Air 4th.
The A14 Bionic is a 64-bit ARM-based SoC with 6-CPU in a big.LITTLE configuration, 4-GPU plus a new 16-core Neural Engine. According to Apple’s statement, the A14 is the fastest smartphone chip ever, and 40% faster than the previous generation. The chip has 11.8 billion transistors and was fabricated by TSMC on 5nm process. This manufacturing process is also applied on Apple’s M1.
The A14 SoC side contains SRAM cache in the die and integrates external LPDDR4X DRAM with packaging. The updated TSMC inFO technology is used for A14’s packaging. To integrate the DRAM die, Apple performed standard PoP technology which includes copper pillar, redistribution layers, and silicon high-density capacitor integration.
In order to reveal every detail of the A14 Bionic, this report features multiple analyses. These include front-end construction analysis to reveal the most interesting features of the TSMC 5nm process, and back-end construction analysis for the packaging structure. This report also provides a detailed study of the SoC die analyses and its cross-sections. Furthermore, along with a complete construction analysis using SEM cross-sections, material analyses, and delayering, we offer a high-resolution TEM cross-section of TSMC’s 5nm from the Apple M1. CT-scan (3D X-ray) is also furnished to reveal the layout structure of the package. Lastly, this report includes a complete cost analysis and a selling price estimation of the component without the main PCB substrate.