ASE/Deca M-Series Fan-Out Process

Back in 2015, only Outsourced Semi-conductor Assembly and Test (OSAT) players were involved in Fan-Out (FO) packaging. But in 2016, TSMC led the entry of foundries into this market. With its integrated FO (inFO) packaging technology, TSMC and Apple introduced the first high density FO package in the mobile segment. Now, Integrated Device Manufacturers (IDMs) like Samsung have joined the race with new in-house technology at the panel level. The result is that in 2019 OSATs have only a third of the market. Even with this reduced share, they are still developing and enhancing their portfolio in this segment. ASE, in partnership with Deca Technologies, has developed FO technology targeting the core market. Formerly a user of Embedded Wafer Level Ball Grid Array (eWLB) packaging, ASE has moved to M-series packaging technology for its advanced Wafer Level Packaging (aWLP).

With production maturity, fabless companies like Qualcomm are seeking yield loss improvements, reducing the number of chipped dies following dicing. FOWLP was eventually adopted as side-wall protection to help manage incoming dies regardless of whether they’re on 200mm or 300mm wafers, which resolved the yield issue. In the past, Qualcomm has used eWLB for side-wall protection for this purpose. But now the M-series technology from Deca Technologies is mature. ASE, the current OSAT supplier for Qualcomm, has switched packaging production.

One of the main advantages of the technology is that at a similar price to the eWLB technology, the M-series offers better quality and board level reliability (BLR). Indeed, one of the key enablers is the use of epoxy molding compound (EMC) between the die and the redistribution layers (RDLs).

This report includes a full investigation of the component, featuring a detailed study of the PMIC including packaging, die design and cross-sections. It contains a complete cost analysis and a selling price estimation of the component. Finally, it features a comparison with the Qualcomm WCD9335 Audio Codec, featuring eWLB packaging.

REVERSE COSTING WITH:

• Detailed photos and cross-sections
• Precise measurements
• Material analysis
• Manufacturing process flow
• Supply chain evaluation
• Manufacturing cost analysis
• Comparison with WCD9335 using eWLB for Side Wall Protection
• Estimated sales price

Overview/Introduction

Qualcomm Company profile and ASE/Deca Roadmap

Samsung Galaxy S10 5G USA Teardown

Market Analysis

Physical Analysis

• Physical Analysis Methodology
• M-Series Packaging Analysis
  • Package view and dimensions
  • Package cross-section: RDLs, UBM, copper studs
  • Package process analysis
• PMIC Die Analysis
  • Die view and dimensions
  • Die delayering and main block IDs
  • Die cross-section
  • Die process

Manufacturing Process Flow

• PMIC Die Process and Fabrication Unit
• M-Series Packaging Process Flow and Fabrication Unit

Cost analysis

• Overview of the Cost Analysis
• Supply Chain Description
• Yield Hypotheses
• PMIC Die cost Analyses
  • Front-end cost
  • Wafer and die cost
• M-Series Package Cost Analysis
  • Packaging front-end cost
  • Packaging cost by process step
• Final Test Cost
• Component Cost

Estimated Price Analysis

Comparison between eWLB and M-Series for Side Wall Protection