Technology, Process and Cost

Goodix GSN22 in Honor 500

How Goodix builds a secure, compact NFC + eSE: dual-die teardown, CMOS processes, and end-to-end cost analysis.

SPR26069

SCOPE

Analyzed devices: Goodix GSN22

From module/end system : Honor 500

 

PHYSICAL ANALYSIS

  • Detailed photos in optical and SEM views
  • Precise measurements
  • Package opening
  • ASIC delayering
  • Material identification

Technology 

  • NFC controller and Embedded Secure Element
  • CMOS  (Logic, Analog, SRAM, ROM)

Type of Analysis

  • SEM View
  • Floorplan
  • FIB Cross section
  • Delayering
  • Optical View
  • X-ray View

 

MANUFACTURING PROCESS FLOW

  • Recreation of manufacturing process flow
  • Step by step process flow

Technical analysis

  • Module​
  • Component​
  • Process​
  • Wafer​
  • Material​
  • IP
  • Packaging
     

COST ANALYSIS

  • Supply chain evaluation
  • Simulation of device cost
     

Type of Analysis

  • Die cost
  • Yields
  • Package assemble cost
  • Raw wafer cost
  • Wafer Front-End cost
  • Die cost
  • Dicing & Probe test cost
  • Package assemble cost
  • Final test cost

 

REPORT'S OBJECTIVES

  • Provide a physical and cost analysis of the Goodix GSN22 integrated NFC + eSE solution. 
  • Analyze the package construction and multi-die assembly, from external dimensions down to die-level architecture and interconnects. 
  • Present the manufacturing process and technology for each die at every level (package, die, functional block, metallization stack, process node). 
  • Provide a reverse-costing breakdown of the component, from finished package down to front-end wafer, and estimate the resulting manufacturer selling price.

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