Google Tensor Pixel 6 SoC

Google’s Tensor SoC brings yet another player into the competitive field of smartphone design. This industry segment generated $35B in revenue for smartphone designers in 2021, and Yole Développement’s market analysis expects the smartphone processor market to reach $41B by 2026.
This full reverse costing study provides insight regarding technology data, manufacturing cost, and selling price of the Google Tensor system-on-chip (SoC).
In 2021, Google published its first smartphone processor, Tensor SoC, to power the Pixel 6 and Pixel 6 Pro. The software giant has now joined the global game of chip manufacturing, competing with big players like Apple, Samsung, and Qualcomm.
Google developed the Tensor SoC based on ARM architecture. This SoC is equipped with two big ARM X1 cores, two Cortex-A76, four Cortex-A55, a 20-core ARM Mali-G78 GPU, and Google’s custom-made TPU (Tensor Processing Unit) to boost its machine learning models. To further increase the power efficiency, Tensor also includes its own advanced image signal processor (ISP) and an ultra-low-power engine. The chip is fabricated by Samsung on 5nm process technology, which is also used to manufacture several competitive SoCs such as the Qualcomm Snapdragon 888 and Samsung Exynos 2100.
The Google Tensor SoC contains SRAM cache on the die and integrates an external LPDDR5 SDRAM with packaging. The PoP ball-grid array packaging is applied to assemble the whole Google Tensor SoC chip. The PoP technology stacks the DRAM on top of the SoC.
To reveal all the details of the Google Tensor chip, this report features multiple analyses: a front-end construction analysis to reveal the most interesting features of the Samsung 5nm process, and a back-end construction analysis for packaging structure. This report also features a detailed study of the SoC die with cross-section analyses. In addition to a complete construction analysis using SEM cross-sections, material analyses, and delayering, we show a high-resolution TEM cross-section of Samsung’s 5nm from the Exynos 2100. A CT-scan (3D X-ray) is also provided to reveal the layout structure of the whole chip package. Moreover, the floor plan of the SoC die is included in order to give a clear view of IP blocks and general chip architecture. Lastly, this report contains a complete cost analysis and selling price estimation of the Google Tensor chip.

Overview / Introduction

• Executive Summary
• Product Brief
• Reverse Costing Methodology
• Glossary

Company Profile

• Company Profile
• Google Pixel Series
• Market Analysis

Physical Analysis

• Smartphone Teardown
• Google Tensor Package Analysis
  • Views & Dimensions
  • CT-Scan Image
  • Cross-Section
• DRAM Die
  • View & Dimensions
  • Cross-Section
• Google Tensor SoC Die
  • Views & Dimensions
  • Delayering
  • Die Process
  • Die Cross-Section
• 5nm process FEOL

Floor Plan

• Manufacturing Process
• Global Overview
• SoC Die Front-End
• SoC Die Wafer Fabrication Unit
• SoC Die Packaging Process

Cost Analysis

• Cost Analysis Summary
• Yields Explanation & Hypotheses
• SoC Wafer Cost
• SoC Die Cost
• SoC Packaging Cost
• SoC Component Cost

Selling Price

Feedback

Related Analysis

System Plus Consulting Services

Product’s key features:

• Detailed photos
• Precise measurements
• Front-end structural analysis with TEM
• Back-end structural analysis with CT scan
• Floorplan
• Materials analysis
• Manufacturing process flow

Available on our Yole Group All-Inclusive Computing Package