Market and Technology Trends

High-End Performance Packaging 2022 – Focus on 2.5D/3D Integration

By Yole Intelligence — Mar 2022

High-performance computing and ADAS are driving the growth of 3D performance packaging, requiring a development platform for new technologies and reaching $7.87B in 2027.

What’s new:

More products commercialized
Updated number of dies per package
Updated die dimensions
Updated package dimensions
Updated wafer-start figures
More information available on new high-end performance packages
Updated ASP in some situations due to a general price increase (i.e., TSMC increased its FE price by 20% approximately)

Why do We Need High-end Performance Packaging?

As front-end node becomes smaller, design cost is becoming more and more important. Advanced packaging (AP) solutions help solve these issues by reducing the cost while at the same time enhancing system performance and presenting lower latency, increased bandwidth, and power efficiency.

High-end Performance Packaging platforms are UHD FO, embedded Si bridge, Si interposer, 3D stack memory, and 3DSoC. Embedded Si bridge has two solutions: LSI from TSMC and EMIB from Intel. For Si interposer, there is a classic version usually provided by TSMC, Samsung, and UMC, and an active one which is Intel’s Foveros. EMIB combined with Foveros gives birth to Co-EMIB, which is used for Intel’s Ponte Vecchio. Meanwhile, 3D stack memory is represented by three categories: HBM, 3DS, and 3D NAND stack.

Datacenter networking, high-performance computing, and autonomous vehicles are pushing the adoption of high-end performance packaging, along with its evolution from a technology point of view. Today the trend is to have bigger computing resources at cloud, edge computing, and device level. Therefore, an increasing demand is fueling High-end Performance Packaging adoption.

High-End Performance Packaging Market Size?

High-end Performance Packaging market revenue is forecast to reach $7.87B by 2027, up from $2.74B in 2021 and with a CAGR2021-2027 of 19%. UHD FO, HBM, 3DS, and active Si interposer are considered to represent more than 50% of combined market share by 2027, being the biggest contributor to market growth. Embedded Si bridge, 3D NAND stack, 3D SoC, and HBM are the top four fastest-growing contributors, each with a CAGR bigger than 20%. This evolution is possible due to the rapid growth of high-end performance applications and artificial intelligence in the telecom & infrastructure and mobile & consumer end-markets. High-end Performance Packaging represents a relatively small business, but with a huge impact on the semiconductor industry as it is one of the key solutions helping to meet More-than-Moore requirements.

Who are the Winners, or Losers?

In 2021, CapEx investments of about $11.6B were made for package activity by top players, as they are conscious about its enormous importance for fighting the slowdown of Moore’s Law.

Intel is the top investor, with $3.5B. Its 3D chip stacking technology is Foveros, which consist of stacking a die on an active silicon interposer. Embedded multi-die interconnect bridge is its 2.5D packaging solution utilizing 55-micron bump pitch. The combination of Foveros and EMIB gives birth to Co-EMIB, used for Ponte Vecchio GPU. Intel plans to adopt hybrid bonding technology for Foveros Direct.

TSMC is following through with $3.05B of CapEx. While securing more business for UHD FO with its InFO solutions, TSMC is also defining new system-level roadmaps and technology for 3D SoC. Its CoWoS platform is offering solutions as RDL or silicon interposers, while its LSI platform is a direct competitor for EMIB. TSMC has emerged as a High-end Packaging powerhouse with leading FE advanced nodes allowing to dominate next-generation system-level packaging.

Samsung has its I-Cube technology, which is similar to CoWoS-S. Samsung is one of the 3D stack memory solution leaders, providing HBM and 3DS. Its X-Cube will use hybrid bonding interconnect.

Boasting a U.S. $2B estimated CapEx, ASE is the biggest and only OSAT trying to compete with foundry and IDMs for packaging activity. With its FoCoS product, ASE is also the only OSAT with a UHD FO solution at the moment.

OSATs don’t have the financial and front-end capabilities to keep pace with big players like Intel, TSMC, and Samsung in the advanced packaging race. Therefore, they are followers.

Objectives of this report

Key features of this report

Report methodologies & definitions

About the authors

Yole Group of companies related reports

Glossary

Companies cited in this report

What we got right, what we got wrong

3-Page summary

Executive summary

Context

Semiconductor industry – players pursuing Moore’s Law
High-end performance packaging definition
Packaging technologies: scope of report
High-end performance packaging market segmentation
High-end performance packaging introduction

Market forecasts

Package ASP split by technology
Market forecast – 2020 VS 2022
Revenue
- Total market revenue
- Split by end-market
- Split by technology
Market size – units
- Total market units
- Split by end-market
- Split by technology
Market size split by technology
- 3D SoC
- 3D stacked memory
- 2.5D interposers
- UHD FO
- Embedded Si Bridge
Chapter conclusion

Market trends

Datacenter; networking
Autonomous vehicles
Chapter conclusion

Commercialization, players & supply chain

Product launches
- 3D stacked memory
- (x)PU
- HPC
- GPU for HPC
Supply chain for high-end performance packaging
- Global mapping of high-end packaging
- Global mapping based on technology
- Supply chain for high-end packaging products
Latest progress of key players
Supply chain analysis in high-end performance packaging
- Packaging supply chain analysis
Analyst’s point of view on supply chain
- High-end Performance Packaging – supply chain status
- It is a new battlefield for technology supremacy
- Impact within big players
- Impact on OSATs & substrate suppliers
- What makes ASE different from other OSATs
- This is an endeavor to dominate the entire high-value manufacturing business
- Who are the winners/losers?
Chapter conclusion

Hybrid bonding

Adoption and trends
Technology
Supply chain
Key players
IP landscape
Conclusion

Technology trends

Technology roadmap
- Semiconductor packaging roadmap
- Advanced packaging roadmap
- High-end packaging technology roadmap: IO pitch vs IO density
- High-end packaging roadmap: application-technology
Key players’ technology roadmaps
Short description of chiplet
3D SoC
TSV process
3D stacked memory
- HBM
- 3D Stacked DRAM (3DS)
- Hybrid bonding
2.5D interposer
Ultra-High-Density Fan-Out (UHD FO)
Embedded Si Bridge
Other high-end packaging technologies
Chapter conclusion

Report conclusion

Appendix

DIRAM stacked memory

About Yole Développement

Key Features:

From a financial point of view, all $ are U.S.
Yole’s definition of High-end Performance Packaging
High-end Performance Packaging market segmentation
Market valuation in terms of package units, revenue, and wafer production volumes
Market valuation of key High-end Packaging technologies
High-end Performance Packaging market trends: end-system drivers
Commercialization of High-end Performance Packaging products
Global mapping of High-end Performance Packaging supply chain
Supply value chain analysis in High-end Performance Packaging
Application-technology roadmap of High-end Performance Packaging
Key players’ technology roadmaps for High-end Performance Packaging: Intel, TSMC, and Samsung
IP analysis: 3D SoC – hybrid bonding

Available on our Yole Group All-Inclusive Semiconductor Packaging Package

Do you have an account?

Search