HiSilicon Kirin 9000 SoC

HiSilicon’s Kirin 9000 has arrived as a highly competitive processor in an industry estimated to have generated $35B in revenue for Smartphone designers in 2021.  Yole Développement’s market analysis expects the smartphone processor market to reach $41B by 2026.

This full reverse costing study was conducted to provide insight regarding the technology data, manufacturing cost, and selling price of the Kirin 9000 system-on-chip (SoC).

HiSilicon is Huawei’s design center and is also the biggest Chinese IC designer and developer of cutting-edge semiconductor technology. Processors are one of HiSilicon’s main products. The company develops multiple series of SoCs based on ARM architecture for smartphone, tablet, wearable devices, and AI acceleration chips. Among its processor series, the Kirin series is mainly used for smartphone applications.

The Kirin 9000 is the most advanced generation to support the Huawei Mate 40 Series and part of the Huawei P50 Pro smartphone. This latest chip is equipped with four ARM Cortex-A77 CPUs, four ARM Cortex-A55s, and a 24-core ARM Mali-G78 GPU, plus Huawei Ascend Lite and Da Vinci Architecture 2.0 to activate its AI power. The chip has 15.3 billion transistors and is fabricated by TSMC on 5nm process, which is also used to manufacture several rival SoCs such as the Apple A14, Apple M1, and Apple A15.

The Kirin 9000 SoC contains a SRAM cache in the die and includes an external LPDDR5 or LPDDR4X DRAM with packaging, depending on the smartphone model. The advanced PoP ball-grid-array packaging technology is applied for integrating the SoC die and DRAM die in one chip.

To reveal all the details of the Kirin 9000, this report features multiple analyses. One is a front-end construction analysis to reveal the key features of the TSMC 5nm process, and another is a back-end construction analysis for packaging structure. Also featured is a detailed study of the SoC die analyses and its cross-sections. In addition to a complete construction analysis using SEM cross-sections, material analyses, and delayering, we show a high-resolution TEM cross-section of the TSMC 5nm from the Apple M1. CT-scan (3D X-ray) is also provided to reveal the layout structure of the SoC die package. Moreover, the floorplan of the SoC die is included in order to provide a clear view of IP blocks. Lastly, this report furnishes a complete cost analysis and a selling price estimation of the Kirin 9000 SoC die.

Overview / Introduction

• Executive Summary
• Product Brief
• Reverse Costing Methodology
• Glossary

Company Profile

• Company Profile
• Smartphone Application Processor
• Market Analysis

Physical Analysis

• Smartphone Teardown
• Kirin 9000 Package Analysis
  • Views & Dimensions
  • CT-Scan Image
  • Cross-Section
• DRAM Die
  • Views & Dimensions
  • Cross-Section
• Kirin 9000 SoC Die
  • Views & Dimensions
  • Delayering
  • Die Process
  • Die Cross-Section
• 5nm Process FEOL
  • Summary
  • TEM Along PMOS Fin
  • TEM Across Fin

Floorplan

Manufacturing Process

• Global Overview
• Kirin 9000 SoC Front-End
• Kirin 9000 SoC Wafer Fabrication Unit
• MCeP Packaging Process

Cost Analysis    

• Cost Analysis Summary
• Yields Explanation & Hypotheses
• Kirin 9000 SoC Wafer Cost
• Kirin 9000 SoC Die Cost
• MCeP Packaging Cost
• Component Cost

Selling Price                                                   

Feedback                                                           

Related Analysis                                                             

System Plus Consulting Services              

Key features of the report:

• Detailed photos
• Precise measurements
• Front-end structural analysis with TEM
• Back-end structural analysis with CT scan
• Floorplan
• Materials analysis
• Manufacturing process flow
• Supply-chain evaluation
• Manufacturing cost analysis

Available on our Yole Group All-Inclusive Computing Package