Kioxia/Western Digital 112-layer 3D NAND Memory

• Western Digital
• Kioxia

Demand for datacenter SSD is growing stronger, and smartphone bit demand continues to grow too, driven by 5G and increasing mobile storage requirements. NAND memory revenue is expected to exceed 80B in 2022. Kioxia’s NAND market share was estimated at 18% in 2021, with 15% for Western Digital.  

The introduction of BiCS5 NAND memory targets data-centric client electronics, smartphones, and artificial intelligence (AI), including datacenter applications. BiCS5 is the second generation from the Kioxia and Western Digital joint venture. Built by string stacking, this 3D flash memory features a two-tier NAND array architecture. It is a vertically stacked NAND array structure – the vertical scaling method allows Kioxia/Western Digital to increase the NAND memory density by approximately 20% compared to the previous BiCS4. With 96 active layers, the layer increase results in higher bit production per wafer, as well as cost reduction. Western Digital claims that the new BiCS5 design enables accelerated memory performance, enabling higher data transfer speed compared to BICS4. The design uses periphery on the side, which occupies a significant area on the NAND memory die.

This report includes an overview of the 256GB NAND memory package, with a teardown revealing four stacked NAND memories in a BGA package. This report also analyses Kioxia/Western Digital’s 512Gb 3D NAND die, a memory which uses triple-level cell storage. This full physical analysis is accompanied by optical images and high-resolution SEM images of both the package cross-section and die cross-section. From the package cross-section, the die assembly is revealed. Meanwhile, two different die cross-sections disclose the CMOS transistor position, NAND array, and cell memory storage. The cross-section analysis focuses on the NAND memory channel-hole structure and the storage layers and material.  The material used in the manufacturing process is identified by an EDX analysis. The top metal layers and the NAND array region are removed to reveal the CMOS transistor technology. Also provided in this report are the manufacturing process of the 112-layer NAND memory and the final package assembly. Lastly, a cost analysis furnishes an estimation of Kioxia/Western Digital’s TLC, NAND memory wafer cost, die cost, and component cost.

Overview / Introduction

• Executive Summary
• Reverse Costing Methodology

Company Profile

• Executive Summary
• Reverse Costing Methodology

Market Analysis

• Executive Summary
• Reverse Costing Methodology

Physical Analysis

• Summary of the Physical Analysis
• Memory Package
  • Package Views & Dimensions
  • Package Cross Section
  • Package Opening
• Memory Die
  • Memory Die View & Dimensions
  • Memory Die Cross-Section
  • Memory Die Delayering
  • Memory Die Process Characteristic

Memory Manufacturing Process 

• Memory Die Front-End Process
• Memory Fabrication Unit
• Final Test
• Summary of the main parts

Cost Analysis

• Summary of the cost analysis
• Yields Explanation & Hypotheses
• Memory die
  • Memory Die Front-End Cost
  • Memory Die Probe Test, Thinning & Dicing
  • Memory Die Wafer Cost
  • Memory Die Cost
• Complete Component
  • Packaging Cost
  • Component Cost

Selling price

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