Market and Technology Trends

Panel Level Packaging 2026

Mar 2026

PLP market set to grow more than 40% CAGR to 2031, driven by UHD FO/2.5D for AI, HPC, and chiplet architectures.

YINTR26542

PLP generated over $300M in revenue in 2025 and is projected to grow at a >40% CAGR over the next five years. PLP is set for strong acceleration toward 2029-2030, driven by TSMC’s entry and the adoption of high-end PLP for AI and HPC applications.

The PLP supply chain is attracting a wide range of business models. Early pioneers such as SiPTORY, Samsung Electronics, PTI, and SiPLP established initial production. Since then, major OSATs and new entrants have joined the market.

PLP is emerging as a cost-efficient alternative to wafer-level packaging while also offering a pathway to replace traditional packages. Its developments are progressing along low- to mid-end fan-in/fan-out solutions and high-end fan-out platforms.

What's new

Updated area and cost-efficiency studies for different panel sizes: 310x310 mm, 515x510 mm, 600x600 mm, and 700x700 mm.
Market sizing update based on the latest production and capacity inputs from PLP players, with forecasts extended to 2031.
Panel volume forecast with a breakdown by panel size and technology type (Fan-In, Core FO, HD FO, and UHD FO/2.5D).
Evaluation of the impact of increasing adoption of UHD FO/2.5D panel-level interposers on the overall PLP market forecast.
Analysis of the impact of TSMC entering the PLP supply chain with its CoPoS technology, expected to start production by the end of the decade.
2025 PLP manufacturer market shares, highlighting the role of emerging companies in the low- to mid-end PLP segment.
Analysis of panel sizes used by different companies, with segmentation by applications and market segments.
More in-depth analysis of the PLP equipment ecosystem, including comparison of available plating systems, and identification of key metrology and inspection requirements.
Analysis of materials used in PLP, such as dry films vs. liquid dielectrics and different types of encapsulation mold compounds.
Overview of panel-level packaging alliances and partnerships.
Technology comparison and introduction timelines for competing approaches: CoWoS vs. CoWoP vs. CoPoS.
Analysis of the potential advantages and use cases of PLP for Co-Packaged Optics.
Description of new PLP players’ technologies and roadmaps, including ASE, SiPTORY, EMCT, and TSMC.

Report’s objectives

The main objectives of this report are:

To identify and describe which technologies can be classified as ‘Panel Level packaging’ (PLP) and define technology sub-segments
To analyze key market drivers, benefits and challenges of PLP packages for the different applications
To describe the different existing technologies, their trends and roadmaps
To analyze the supply chain and PLP packaging market landscape
To provide a market forecast for the coming years, and estimate future trends

Panel level Packaging markets are studied through the following analysis:

Top-down model based on end-system demand and market valuations based on top-down and bottom-up models
Market share based on production projections
Supply value chain analysis
State-of-the-art technologies and trends
End-user adoption for the various applications
Transition from Wafer-Level Packaging to Panel Level Packaging

Panel Level Packaging market is set to grow with more than 40% CAGR

Panel-Level Packaging (PLP) generated over $300M in revenue in 2025 and is projected to grow at a >40% CAGR over the next five years to reach almost $3B. While still a small share of the advanced packaging market, PLP is set for strong acceleration toward 2029-2030, driven by TSMC’s entry and the adoption of high-end PLP for AI and HPC applications.
Today, PLP demand is led by the mobile and consumer sectors, followed by telecom & infrastructure, automotive, and industrial markets. Key devices include APUs, PMICs, RF ICs, audio codecs, MCUs, and other analog and power ICs.
Technology adoption is expanding rapidly. FIPLP ramped in 2024, driven by STMicroelectronics for RF devices. Core FO reached ~20% of the market in 2025, replacing FOWLP, WLCSP, and QFN with a more cost-efficient approach. HD FO currently leads the market, supported by Samsung’s HD FO PoP for mobile and wearable APUs. Meanwhile, UHD FO and 2.5D interposers are emerging and are expected to become the largest PLP revenue driver by 2031.
Strong industry-wide investments across Fan-In, Core, HD, and UHD FO/2.5D technologies are fueling capacity expansion and positioning PLP as one of the fastest-growing segments in advanced packaging.

PLP supply chain is attracting different business models

The PLP supply chain is rapidly expanding and attracting a wide range of business models across the semiconductor ecosystem. Early pioneers such as Samsung Electronics, PTI, SiPTORY and SiPLP established initial production for mobile and power devices, paving the way for broader adoption.
Since then, major OSATs and new entrants, including ASE, Silicon Box, STMicroelectronics, and ECHINT, have joined the market, targeting both high-volume cost-driven applications and high-end advanced packaging. Mainland China hosts more PLP manufacturers and emerging players than other regions.
Today, two complementary PLP segments are emerging. The low- to mid-end segment focuses on cost-efficient packaging for power ICs, RF, and analog devices, while the high-end segment targets AI, HPC, networking, and chiplet-based architectures, requiring larger panels and advanced integration.
This momentum is attracting diverse players from OSATs, substrate manufacturers, WLP providers, and even LCD supply chains. Equipment and materials suppliers are also expanding their offerings, adapting to the industry’s different panel sizes.

PLP technology roadmap towards high-end packaging fueled by AI

PLP is emerging as a cost-efficient alternative to wafer-level packaging for technologies such as WLCSP, fan-out, and organic 2.5D interposers, while also offering a pathway to replace traditional packages like leadframe-based QFN for RF, power, and MCU devices. As a result, PLP development is progressing along two main segments: low- to mid-end fan-in/fan-out solutions and high-end fan-out platforms, with large, high-end packages expected to drive the majority of future market revenue.
The rapid growth of chiplet architectures and heterogeneous integration, particularly in AI and datacenter applications, is pushing package sizes beyond the limits of wafer-based processing. By leveraging larger carrier formats, PLP significantly improves area utilization and manufacturing efficiency, enabling 10-30% cost reductions for advanced fan-out interposers while supporting larger, more complex packages.
At the same time, PLP offers a cost-optimized solution for simpler devices, enabling substrate- and leadframe-free architectures with improved electrical and thermal performance. Despite its strong potential, PLP adoption still requires further process maturity, investment, and industry standardization, particularly around panel sizes and large-panel manufacturing challenges.

Glossary
ID Card
About The Authors
Companies Cited
What we got right, what we got wrong
Definitions
Scope of the report
Three-Page Summary
Executive Summary
Context

Overview of the Advanced Packaging Market Trends
Definition of Panel Level Packaging
Panel Level Packaging Motivations

Market Forecasts

Market Forecast Comparison 2025 vs. 2026
Panel Level Packaging Addressable Market
Panel Level Packaging Revenue Forecasts
- By Package Type: Fan-out vs. Fan-in
- By End-Market
- By Technology: Core FO vs. HD FO vs. UHD FO vs. Fan-in
- By Carrier Size
Panel Level Packaging Volume Forecasts – Units & Panels
- By Package Type: Fan-out Vs. Fan-in
- By End-market
- By Technology: Core FO vs. HD FO vs. UHD FO vs. Fan-In
- By Carrier Size
- By Carrier Types: Organic, Metal, Glass

Market Shares

PLP Manufacturer Market Share
Market Share By Technology
PLP Panel Production By Manufacturer

Supply Chain

Supply Chain Overview
PLP Entry Strategies
Business models and manufacturing approaches
PLP Manufacturers Map By HQ and Fab Location
PLP Manufacturers By Technology Type
PLP Key Supplier Activity Summary
PLP Players And Customers Known Relationships
Panel Carrier Size By Manufacturer
Focus on Great China Mainland
Top Investments & News in Panel Level Packaging
Panel Level Packaging Alliances or Partnerships
Panel Level Packaging Standardization
Panel Level Packaging Equipment Supply Chain
- Equipment Suppliers
- Suppliers By Panel Size
- Horizontal vs. Vertical Plating
- Metrology and Inspection Needs
Panel Level Packaging Materials Supply Chain
- Material Suppliers
- Polymeric Materials Trends For PLP
- Dielectric Materials: PSPI vs Dry film
- Mold Compound Trends
- Materials Challenges

Technology Trends

Panel Level Packaging Key Technology Trends
High-end FOPLP & 2.5D Interposers
Low To Mid-end FO/FIPLP for Power & Analog
Panel Level Packaging Technology Roadmaps
Panel Level Packaging Process Flows
Panel Level Packaging Technology Licensers
Panel Level Packaging Technology By Manufacturers
- Powertech Technology (PTI)
- Samsung Electronics
- SiPLP
- STMicroelectronics
- Innolux
- AOI Electronics
- Amkor
- ASE
- ECHINT
- SiPTORY
- EMCT
- TSMC
- Toppan