Technology, Process and Cost

Samsung FO-PLP for Google Pixel 7 Tensor G2 SoC

By Yole SystemPlus — May 2023

A full physical and cost analysis of Google’s self-developed smartphone processor, as well as a comparison of high-end smartphone SoC packaging technologies

SPR23733

Key Features

Google Pixel 7 smartphone teardown
Detailed photos
Precise measurements
Front-end structural analysis with scanning electron microscopy
Transmission electron microscopy analysis of Samsung’s 5 nm FinFET
Floorplan
Comparison of high-end smartphone SoC packaging technologies
Comparison of packaging, die, and floorplan between Tensor G2 and Tensor G
Manufacturing process flow
Manufacturing cost analysis

What's new

The newest generation of Google’s high-end smartphone processor
New die architecture that boosts chip efficiency, security, and image processing
The first smartphone SoC assembled using Samsung’s FO-PLP technology

APUs with fan-out PoP represented 64% of the total fan-out market in 2022, dominating the fan-out market in terms of application types. Revenues for APUs with fan-out packaging will grow at a CAGR2022 - 2028 of 7%, rising from $1.2B in 2022 to $1.6B in 2028.

This full reverse costing study was conducted to provide insight regarding the technology data, manufacturing cost, and selling price of the Google Tensor G2 system-on-chip (SoC), with a focus on the Samsung FO-PLP advanced packaging. This report also includes a comparison of high-end smartphone SoC packaging technologies: FO-PLP, InFO, standard PoP, and MCeP.

Google started developing its high-performance SoC (called Tensor G) for its own Pixel series smartphone in 2021. In 2022, the second-generation Tensor G2 was released. According to Google, the Tensor G2 SoC has several improvements compared to its predecessor, including power efficiency, security, and image processing. The SoC die was made using Samsung’s 5 nm FinFET technology (similar to the Tensor G), but the die assembly was changed to fan-out panel level packaging (FO-PLP). The SoC die contains SRAM caches and includes an external LPDDR5X DRAM package, which is stacked on the SoC die package with PoP (package-on-package) technology.

This report begins with a smartphone teardown of the Google Pixel 7 Pro to show how the Google Tensor G2 and the components around it are integrated on the main board of the phone. Multiple analyses, ranging from FEOL and back-end construction to SoC assembly, are provided. We have also conducted a detailed study of the chip packaging and the SoC die cross-section by using optical microscopy, SEM, material analyses, and delayering. The Samsung 5nm FinFET structure is revealed through high-resolution TEM analysis and then compared with TSMC’s 5nm technology. In addition, a CT-scan (3D X-ray) is used to show the layout of the SoC die package, while a floorplan study of the SoC die presents a clear view of the IP design. Furthermore, we compare the physical structure of FO-PLP with three other high-end smartphone SoC packaging technologies: standard PoP, TSMC integrated fan-out (InFO), and molded core embedded package (MCeP). A comparison of the SoC die and the floorplan between Tensor G2 and Tensor G is also included. Lastly, this report furnishes a complete cost analysis and a selling price estimation.

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Samsung FO-PLP for Google Pixel 7 Tensor G2 SoC

A full physical and cost analysis of Google’s self-developed smartphone processor, as well as a comparison of high-end smartphone SoC packaging technologies