Sony Event based CIS - IMX646

SCOPE

Analyzed component : Sony Event Based Vision - CMOS Image Sensor

 

PHYSICAL ANALYSIS

Physical analysis of Sony Event-based Vision CIS, including cross-sectional imaging of the package and detailed cross-section and delayering analysis of the CIS die.

Technology:

• Event Based 
• Vision
• Neuromorphic
• BSI
• Cu-Cu Bonding
• F-DTI

Technical analysis:

• Module
• Die
• Process
• Material

 

MANUFACTURING PROCESS FLOW

We describe the process flow of the logic and pixel dies of the stacked CIS.

Type of Analysis:

• Opening
• Cross section
• SEM View
• Optical View
• IR View
• Delayering

 

COST ANALYSIS

Cost analysis of the Sony Event-based Vision CIS IMX646, including a detailed front-end and back-end cost breakdown.

Type of Analysis:

• Yields
• Front End Cost
• Die Cost
• Back End Cost

 

PRODUCT'S OBJECTIVES

• Present technology and cost analysis on the Sony IMX646 event-based vision CIS, co-developed with Prophesee.
• Follow the main technological developments in the field of event-based (neuromorphic) vision.
• Provide new insights about event-based CMOS Image Sensors from Sony.

With a 50% share of the CMOS image sensor market, according to our Status of the CMOS Image Sensor Industry 2026  report, Sony remains the undisputed industry leader. Beyond its dominance in mobile and automotive imaging, Sony has also pioneered an entirely new sensing paradigm through its Event-based Vision Sensor (EVS) line, co-developed with Prophesee, combining Sony's stacked CMOS image sensor technology with Prophesee's event-based Metavision® sensing method. the IMX646, embody this collaboration and stand as the reference commercial event-based sensor, moving neuromorphic vision from laboratory curiosity to production-ready deployment.

This report explores the architecture and cost breakdown of Sony's event-based sensors by presenting findings from in-depth physical analyses and cost assessments of the IMX646 CMOS Image Sensors. The physical analysis includes the complete structure, design, and teardown of the stacked sensor. It describes the pixel and logic tier dimensions, technology nodes, and the Cu-Cu hybrid bonding stacking.

The IMX646 EVS packaged in LGA 156 pins stands out with a two-tier architecture that separates function from sensing: a back-illuminated pixel tier, built on a mature node and optimized for a 4.86 µm event-driven pixel, is bonded to a dedicated logic tier fabricated on an 40nm technology node, carrying the readout, arbiter, event encoder, and dual MIPI/SLVS output interface. This partitioning lets each tier be optimized independently — the pixel for dynamic range and low-light response, the logic for asynchronous readout and event compression and reflects Sony's broader strategy of pushing stacked manufacturing toward ever more specialized sensing applications.

Overview / Introduction                                

• Executive Summary
• Reverse Costing Methodology
• Glossary

Company Profile,  Supply Chain & Market             

• Sony, Prophesee
• Players & Market Context
• Supply Chain
• Technical Data from datasheet

Physical Analysis                            

• SUMMARY of the physical analysis
• IMX646 Package 
  
  • Overview & Dimensions
  • Package Opening
  • Package X-RAY
  • Package Cross Section 
• IMX646 Die
  
  • Overview & Dimensions
  • Die Cross Section
  • Pixel EDX
  • Die IR View
  • Delayering & Main Blocks

Manufacturing Processes    

• Global View & Supply Chain
• Front-End Fabrication Unit
• Main Front-End Wafer Fabrication Steps

Cost Analysis

• Yields Synthesis
• Yield Hypotheses
• CIS Die Front-End
• CIS Die Cost
• Packaging Cost
• Component Cost
• Component Price

Yole Group Related Products

Prophesee, Sony, TSMC