YMTC 3D NAND 128 layers

Key Features

• Detailed photos
• Precise measurements
• Materials analysis
• Manufacturing process flow
• Supply chain evaluation
• Manufacturing cost analysis

Available on our Yole Group All-Inclusive Semiconductor Packaging Package

• Yangtze Memory Technologies Corp YMTC
• Xinxin Semiconductor Manufacturing Corporation XMC

Yangtze Memory Technologies Corporation (YMTC) NAND revenue was estimated at $1.3B dollars in 2021, with NAND revenue market share estimated at ⁓2%. YMTC penetrated the NAND memory market in 2020 and has the potential to gain significant wafer share and market share in the future. In 2016, YMTC achieved its first 32-layer 3D NAND memory product. To catch up in the competitive memory business, YMTC jumped from 64-layer 3D NAND memory products to 128-layer 3D NAND products, skipping the 96-layer node entirely.
Walt monitor data when released + update the numbers in report too

YMTC’s 128-layer product applies Xtacking 2.0 technology. Independent processing of the CMOS wafer and the NAND array wafer increases throughput and reduces product development time. The memory chip size is reduced more than 20% when the controller logic is placed on a different wafer, compared to placing the controller logic on the periphery. Vertical interconnects are used to join the two wafers through a direct bonding process that requires high alignment accuracy. YMTC launched this new 3D NAND memory using a total of 128 active wordlines, and the NAND array layers are built on two decks. The 3D NAND Xtacking architecture combines the benefits of high-density chips with fast I/O speed. The analyzed chip using YMTC’s 128 layers has a ⁓47% higher density compared to the previous 64-layer NAND chip memory using Xtacking 1.0 technology. The pairing of Xtacking architecture applied in 3D NAND with an increased number of wordlines enables higher array efficiency and a significant density increase. Through silicon via (TSV) technology is used in the manufacturing process of the NAND wafer. The CMOS wafer integrates CMOS transistors, page buffers, a decoder, and SRAM memory.

A full teardown was conducted by System Plus to provide insight on YMTC’s 3rd-generation 3D NAND memory. This includes multiple physical analyses of the memory package and die cross-sections to identify front- and back-end processes, as well as insights regarding the Xtacking technology used to build YMTC’s 128-layer NAND. We also identify the CMOS process technology, the NAND array process, and the bonding process of the two wafers. Moreover, this comprehensive report offers optical, SEM cross-sections, material analyses, and a delayering of the memory die. An estimate of the manufacturing cost of YMTC’s 512Gb TLC die is furnished as well, including the transistor and metal layer wafer cost, NAND array cell, bonding cost, die cost, and packaging cost. Lastly, an estimated component cost is provided.

Overview / Introduction

• Executive Summary
• Reverse Costing Methodology

Company Profile

• YMTC
• 3D NAND History
• Xtacking Technology
• Products

Market Analysis

• NAND Revenue
• Bit Demand
• Market Shares

Physical Analysis

• Summary of the Physical Analysis
• Memory Package
  • Package Views & Dimensions
  • Package Cross Section
  • Package Opening
• Memory Die
  • Memory Die View & Dimensions
  • Memory Die Cross-Section
  • Memory Die Delayering
  • Memory Die Process Characteristics

Memory Manufacturing Process

• Memory Die Front-End Process
• Memory Fabrication Unit
• Final Test
• Summary of the Main Parts

Cost Analysis

• • Summary of the Cost Analysis
  • Yields Explanation & Hypotheses
  • Memory Die
    • Memory Die Probe Test, Thinning & Dicing
    • Memory Die Wafer Cost
    • Memory Die Cost
  • Complete Component
    • Packaging Cost
    • Component Cost

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