Beyond advanced packaging basics: exploring the next frontier in memory

The adoption of hybrid bonding in the latest 3D flash memory device by Kioxia and Western Digital marks a significant point in the evolution of 3D NAND architecture, explains Thibault Grossi, Senior Technology and Market Analyst, Semiconductor & Software Division at Yole Intelligence, part of Yole Group, in the Memory Packaging 2023 report.

Therefore, last month’s announcement from both Kioxia and Western Digital was significant – and timely. This is the eighth generation of BiCS FLASH (BiCS8) and marks an evolutionary stage in advanced packaging for 3D NAND to optimize die efficiency, effectively integrate logic, and add value.

The new BiCS FLASH balances vertical and lateral scaling to increase capacity in a smaller die with higher bit density per layer. The companies have developed CBA (CMOS Bonded Array) technology, exploiting the benefits of bonding separate CMOS wafer and cell array layers for enhanced bit density and fast NAND I/O.

BiCS8 FLASH delivers a 60% improvement in speed, compared to the previous (sixth) generation, a 20% improvement in both write performance and read latency and increases bit density by over 50%. Its introduction is a major step in the adoption of hybrid bonding at a time when NAND market revenue is forecast to drop to US$37 billion in 2023 – a decrease of 37% YoY, according to Yole Group’s NAND Memory Market Monitor. Yole Group’s study also expects CapEx to fall by as much as 40% this year.

Kioxia and Western Digital’s 218-layer 3D flash 1Tb TLC and QLC 3D flash has four planes and is a major step forward in the evolution of packaging technology for 3D NAND. Advanced packaging for 3D NAND has focused on hybrid bonding since it was introduced by the Chinese company, Yangtze Memory Technologies Corp (YMTC), in 2018. Its Xtacking solution is a CBA architecture that bonds two wafers, one with the NAND cell arrays and one with the CMOS logic. The permanent bond forms interconnections with pitches of 10µm and below, with no compromise regarding I/O performance while offering the capability to increase the density per mm².  Subsequent iterations have resulted in further increases in density, speed and power performances. 

A major advantage of the CBA process is that both the CMOS logic and NAND cell array can be produced using the optimal technology for each—no compromises are needed to integrate the two on the same die. The results are improvements in capacity, performance and scalability, which are achieved at a lower cost per bit relative to prior BiCS generations, allowing the companies to capitalize on demand growth across a range of market sectors.

Adoption of hybrid bonding will boost NAND packaging revenue growth at a time when the NAND market outlook is uncertain. Experienced NAND flash watchers will recognize the cyclical nature of the market; indeed, Yole Intelligence’s analyst has forecast that the increase in storage demand will result in a NAND revenue CAGR of 9% between 2022 – 2028.

Optimizing integration of memory array and CMOS logic, is crucial to die efficiency, thereby increasing cost-efficiency in a competitive market. The Kioxia and Western Digital announcement highlights one of the main technological evolution stages for 3D NAND with hybrid bonding and the adoption of CBA (CMOS Bonded Array).

The integration of the NAND array and CMOS to-date have involved either positioning the CMOS next to the cell array (CMOS Next Array or CAN) or positioning the CMOS logic under the NAND array (CUA). Most NAND suppliers initially implemented the CAN approach in their 3D NAND processes before migrating to CUA in subsequent processes. The exception is Micron and Intel (Solidigm), who implemented CUA at the beginning of their 3D NAND roadmaps at 32 layers.

Relative to the CAN approach, placing the CMOS logic underneath the memory array shrinks the NAND the die size, thereby increasing the maximum die (and bits) per wafer. This more efficient process goes by different naming conventions, including the aforementioned CUA by Micron and Intel (Solidigm), PERI Under Cell (PUC) which has been adopted by SK Hynix, and Core Over Peri (COP), which was developed by Samsung.

These monolithic strategies are not ideal for long term, continuous scaling, which leads to next step in the evolution, CBA, where the CMOS logic wafer and NAND array wafer can be produced separately, using the optimized process node for each. 

Hybrid bonding is clearly a common point for all players in the NAND market. Xperi’s spin-off company, Adeia, announced a long-term patent license agreement with Kioxia and Western Digital just days before the two companies made the eighth generation BiCS FLASH announcement.

The transition from monolithic production to hybrid bonding will be expensive, requiring additional investments in new cleanroom space and equipment. Despite the high costs, all major NAND suppliers will likely make transition to CBA in the future as 3D NAND scaling becomes increasing difficult to obtain using traditional approaches.

As predicted in Yole Group’s Memory Packaging 2023 Report, Kioxia and Western Digital are the first major IDMs, after YMTC, to adopt hybrid bonding for mass production of its NAND products. They will not be the last. Adeia has also granted licenses to SK hynix (in 2020) and Micron (in 2022). These two memory providers are expected to adopt hybrid bonding for 3D NAND >300L in 2026. Samsung is expected to introduce the technology for >400L the following year.  YMTC licensed the DBI technology as well in 2021.

Whether licensed or developed internally, Yole Intelligence’s memory team expects all of the major NAND IDMs to adopt hybrid bonding in their manufacturing processes, as it provides a sustainable route for efficient, high performance NAND production. Analysts expect that over 50% of the NAND wafers produced in 2028 will use hybrid bonding which will grow the NAND packaging market to a value of US$8.9 billion by 2028, a CAGR of 24% in the period 2025-2028.

Hybrid bonding is clearly a key component of future NAND scalability. The BiCS8 announcement by Kioxia and Western Digital validates this view and is an early step in the NAND industry’s transition to this scalable, efficient, and cost-effective architecture.

Thibault Grossi is a senior technology and market analyst at Yole Intelligence, part of Yole Group, working with the Semiconductor and Software division. He is a member of Yole’s memory team and is engaged in developing technology, market, and strategic analyses. Prior to Yole, he worked at Schneider Electric as a resident engineer in an EMS in Asia and has occupied different positions within the Electronic procurement organization (PCBA, Software and semiconductor). The semiconductor business has been his focus for the last ten years, first in project procurement and then as category manager for semiconductors and displays. He was in charge of procurement strategy for memory and analog devices, leading global negotiations and cooperation in European design projects. Thibault obtained a master’s degree in electronic and computing science from Pierre and Marie Curie University in Paris in 2006.       

Source: www.yolegroup.com