Breaking the wafer barrier: how advanced packaging is scaling in the AI era

Advanced packaging is rapidly becoming a core enabler of the AI and HPC era, driven by the convergence of three key pillars: panel-level packaging (PLP), back-end equipment innovation, and IC substrates. As system complexity increases and chiplet-based architectures scale, traditional wafer-level approaches are reaching their limits. This shift is pushing the industry toward new manufacturing paradigms that reshape cost structures, performance optimization, and supply chain dynamics.

Yole Group’s analysts highlight three key messages: PLP as a pathway to cost-efficient large-format integration, back-end equipment as a strategic driver of performance and scalability, and IC substrates as both a critical enabler and a bottleneck in today’s ecosystem. Together, these trends reflect a broader architectural shift across the semiconductor industry.

This article is authored by Bilal Hachemi, Gabriela Pereira, and Vishal Saroha, experts in semiconductor packaging and equipment at Yole Group.

This analysis is part of Yole Group’s advanced packaging collection of reports and monitors, providing comprehensive technology, market, and supply chain intelligence to support strategic decision-making. For more in-depth insights, see the reports listed below.

Panel Level Packaging (PLP) is emerging as a key enabler of semiconductor systems, driven primarily by the rapid expansion of AI and high-performance computing (HPC). As chiplet-based architectures and heterogeneous integration become mainstream, package sizes continue to increase, particularly for AI accelerators and datacenter processors. These large systems require advanced 2.5D interposers and high-end IC substrates. But scaling at the wafer level is becoming increasingly inefficient, as larger interposers reduce the possible number of packages per wafer.

PLP offers a compelling alternative by leveraging larger carrier formats to improve area utilization and manufacturing efficiency. For large package sizes, PLP can significantly increase carrier efficiency compared to WLP, enabling cost reductions of 10-20% for 2.5D interposer solutions. This makes PLP particularly attractive for AI and HPC applications, where both performance and cost scaling are critical.

The market is gaining momentum, with revenues over $300 million in 2025 and expected to grow rapidly in the coming years. TSMC’s planned entry with its CoPoS technology around 2029 is expected to mark a turning point, accelerating adoption for advanced AI packages.

PLP development is closely tied to advancements in equipment and IC substrate ecosystems. Equipment suppliers are adapting tools to support larger panel sizes, while substrate and material players are exploring new solutions to enable panel-based interposers. At the same time, companies from the LCD and PCB industries are entering the PLP value chain. Despite its strong potential, challenges remain around process maturity, panel standardization, and large-format manufacturing.

From supporting role to strategic enabler

For years, the focus in chipmaking was almost entirely on front-end process technology. However, this is changing rapidly. Back-end equipment is moving beyond its traditional supporting role and is no longer just the final step in semiconductor manufacturing.

AI and HPC driving new packaging requirements

The demand from AI and HPC is pushing device makers toward architectures with more bandwidth, higher power efficiency, and tighter integration of logic and memory. These demands drive HBM, chiplet-based designs, and heterogeneous integration to the forefront, vastly increasing the strategic importance of the equipment used in assembly, bonding, singulation, and inspection.

This transition is especially visible in advanced interconnect bonding solutions where thermocompression bonding (TCB) and hybrid bonding are becoming critical technologies as interconnect density rises and package architectures become more demanding. HBM continues to raise the bar for stacking precision, thermal stability, and yield control. Chiplet architectures require more accurate die placement and more reliable interconnect formation across increasingly complex package designs, especially as architectures move toward higher I/O density and more demanding interposer and substrate designs.

Equipment vendors aligning with next-generation needs

Increasingly, vendors such as BESI, ASMPT, Hanmi, Kulicke and Soffa (K&S) are aligning their roadmaps with the requirements of next-generation packaging, where TCB has become critical for throughput, cost, and final device performance, while hybrid bonding is emerging as the next major inflection point.

BESI, together with its partner Applied Materials, has emerged as a leader in this field. This collaboration also illustrates a broader trend: the convergence of front-end and back-end technologies to enable the next technological paradigm.

Panel-Level Packaging: extending the manufacturing paradigm

The value proposition of panel-level processing relies on whether equipment suppliers can scale precision and process control across larger formats without compromising yield. It is not just about lowering costs: it is about improving throughput while maintaining the alignment, warpage control, and process uniformity needed for advanced packaging applications.

For this reason, the panel story is also an equipment story as equipment vendors are part of that discussion. Indeed, the transition to larger form factors requires the back-end equipment ecosystem to evolve well beyond conventional wafer-based flows. This is already becoming visible in the equipment ecosystem as K&S is explicitly positioning its TCB technology as a bridge from wafer-level to panel-level packaging, ASMPT is promoting PLP capable placement and processes, and DISCO has continued to extend panel singulation with large panel dicing systems.

Back-end equipment supply chain: a new strategic constraint

Advanced back-end equipment depends on a global network of precision components, motion systems, optics, thermal modules, automation hardware, and specialized materials, which means the industry is increasingly exposed to geopolitical pressure, tariffs, export controls, and regional manufacturing imbalances that can impact lead times and capacity ramps. Companies with resilient supply chains, strong regional support, and the ability to localize service and production are likely to be in a stronger position as packaging demand accelerates.

IC substrates are not just another layer in the system. They are a critical foundation supporting the entire advanced packaging ecosystem.

Until TSMC’s CoPoS reaches commercial scale and PLP platforms achieve the process maturity required for wider adoption in AI and HPC, organic IC substrates remain indispensable. They form the architectural backbone of today’s leading AI accelerators, custom hyperscaler ASICs, and HBM-based systems.

Substrate specifications are escalating faster than the industry’s capabilities were designed to support. Substrate sizes have moved from 100mm in 2023 to more than 200mm on the short-term roadmap; Layer counts are advancing toward 30 and beyond; IO connections per package are reaching half a million. Each increase pushes IC substrate fabrication deeper into more advanced equipment and higher CapEx investment just to keep up. The same precision challenges that back-end equipment suppliers are solving for TCB and hybrid bonding at the die level are being solved simultaneously by IC substrate manufacturers at the package level.

The IC substrate supply chain poses significant risks and vulnerabilities that PLP will potentially inherit. T-glass fiberglass is effectively a monopoly market, with capacity expansion governed by furnace construction timelines that no downstream investment can compress, and normalization deferred to 2027 at the earliest. ABF dielectric films face equivalent concentration risk. These are not procurement challenges: they are architectural constraints on how fast the entire advanced packaging ecosystem can rely on IC substrates today and on panel tomorrow.

The three forces, panel-level packaging, back-end equipment evolution, and IC substrate, are not independent trends converging by coincidence. They are a single architectural shift, advancing on three fronts simultaneously toward a manufacturing paradigm where the boundaries between IC substrate fabrication and panel-level processes become progressively more meaningful.

Advanced packaging is entering a decisive phase, in which system-level integration is decisive. As PLP matures, back-end equipment evolves, and substrate constraints intensify, key questions emerge: how fast can the ecosystem scale, and who will lead this transition?

The answers will shape the future of AI infrastructure. Let’s continue the discussion. What do you see as the next bottleneck or breakthrough in advanced packaging?

Stay tuned on www.yolegroup.com!

Bilal Hachemi, PhD, is a Senior Technology & Market Analyst, Semiconductor Packaging at Yole Group.

He contributes on a day-to-day basis to the analysis of packaging technologies, their related materials and manufacturing processes.

Bilal obtained a PhD in nanoelectronics in 2022 from Grenoble Alpes University (France), and he studied at IAE Grenoble for a master’s degree in management.

Gabriela Pereira is Senior Technology & Market Analyst, Semiconductor Packaging at Yole Group.

Working within the semiconductor packaging activities at Yole Group, Gabriela focuses on advanced packaging platforms, develops technology & market reports, and is engaged in dedicated custom projects.

Gabriela holds a master’s degree in metallurgical and materials engineering from the University of Porto, Portugal.

Vishal Saroha is Technology & Market Analyst, Semiconductor Equipment at Yole Group.

Based in Dresden (Germany), Vishal focuses on developing technology and market products and custom consulting projects in the manufacturing and global supply chain domain.

Vishal holds a master’s in nanotechnology from Katholieke Universiteit Leuven (Belgium) and a bachelor’s in physics from the University of Delhi (India).

Source: www.yolegroup.com