Inspection and metrology catching up for high-density fan-out panel packaging

By Anne Meixner for Semiconductor Enginneering – Soaring AI/HPC device demand is driving leading-edge foundries to support the transition from wafers to panels to accommodate increasingly larger device sizes. But to ensure that panels with multiple redistribution layers are known-good, inspection equipment must cope with shrinking RDL features, smaller bump pitch, and the warpage that comes with panels’ larger form factors. 

Once primarily relegated to small chips, panel-level packaging has become increasingly attractive for AI/HPC device makers as package size grows to 80 x 80mm and beyond. While the thermal management associated with high energy consumption has been a prevailing concern, the insatiable need for more compute power in a single package has reached an area limit. Silicon interposer-based packages are generally limited to 100 x 100mm, the largest size at which yield, lithography, warpage, and cost are reasonable. But with panel-level packaging, form factors will range from 310 x 310 mm to 600×600 mm, which TSMC has said will complement CoWoS, not replace it, in some very large packages. 

However, meeting the interconnect density requirements of high-density fan-out (HDFO) pushes panel manufacturers into new territory. 

“It represents a challenge for PLP manufacturers due to large package sizes, the integration of multiple chiplets or devices in the same package, and more interconnect density enabled by lower pitches, smaller RDL L/S, and more RDL layer count,” said Gabriela Pereira, senior technology and market analyst for semiconductor packaging at Yole Group. 

Fan-out panel-level packaging typically uses a chip-last manufacturing process; hence, the need for inspection to assure known-good panels. To support HDFO, layer count goes from 3 to 9, and trace and bump pitches decrease from 20 to 5 microns. In addition, several industry experts said that manufacturers are targeting 2 micron pitches within the next 5 years…. Full article

Source: semiconductorengineering.com