SiPs: the best things in small packages

By Laura Peters for SEMICONDUCTOR ENGINEERING – Better materials and processes enable smaller, higher performing systems-in-package.

System-in-package (SiP) is quickly emerging as the package option of choice for a growing number of applications and markets, setting off a frenzy of activity around new materials, methodologies, and processes.

SiP is an essential packaging platform that integrates multiple functionalities onto a single substrate, which enables lower system cost, design flexibility, and superior electrical performance through shorter interconnections. SiPs are showing up in 5G, IoT, mobile, consumer, telecom, and automotive apps. Of these, the largest and perhaps most exciting segment is consumer and wearable packages — from smart earbuds to capacitor pain patches — slim, comfortable devices that rapidly deliver the health and fitness data people want.

In many respects, SiP and other types of advanced packaging enable the performance and cost benefits once associated almost exclusively with Moore’s Law. “Through our fan-out combinations, flip-chip, BGA, and embedded solutions, ASE has worked really hard, together with TSMC, to extend the Moore’s Law criteria where we hopefully double performance — maybe not at half the cost, but with a cost benefit,” said Yin Chang, senior vice president of sales and marketing at ASE. “That’s why we introduced the VIP Platform to provide a toolbox of solutions that give architects the highest level of flexibility to create differentiated systems.”

Others agree that advanced packaging plays a key role in improving system performance. “At the end of the day, system-level performance is all that matters,” said David Fried, president of Coventor, part of Lam Research. “We are still pushing up against the power, performance, power, area and cost (PPAC) barriers. We are just pushing on different parameters to keep enhancing system-level performance for as long as the market keeps demanding that we provide additional compute power and memory.”

Package type selection typically comes down to balancing performance and cost. “Flip-chip dominates the RF AiP mmWave market, but there is a trend to develop fan-out AiPs (antenna in packages),” said Stefan Chitoraga, technology and market analyst for Yole Intelligence. “Fan-out advantages include smaller form factor, leveraging high-density RDL, and fine pitch compared to flip-chip. Nevertheless, fan out is still too costly, and there are technical challenges to overcome.”

Such challenges include die shift and warpage, which are being addressed by various tooling and process modifications. [1]

To enable high performance, efficiency, and low cost in a single SiP, engineers are incorporating new molding materials, double-sided SiPs, laser-assisted bonding (LAB), and next-generation flexible substrates in fan-out, flip chip, and embedded SiPs.

SiP in 3D

SiP is part of the industry’s 3D revolution. Along with trends to accommodate more I/Os in finer pitches, there are a number of other efforts to cram more into a package rather than onto a single die. This includes multiple redistribution layers in fan-outs, bridges and interposers to connect different die together, double-sided packages to increase density, and embedded die options to enable faster die-to die processing in smaller profiles that consume less power… Full article.