Tradeshows & Conferences
4th Panel Level Consortium SymposiumSign in for replay
The symposium will discuss the status, progress and limits of Panel Level Packaging with experts from around the globe. Speakers from industry and science will bring you up to date on what has been achieved within PLC2.0, including:
- Market and application trends
- Latest technology results for PLP
- Material, equipment and process developments for large area and fine line processing
- Cost analysis
Yole Intelligence powered by Yole Goup will be part of the program
Gabriela PEREIRA, Technology & Market Analyst – Advanced Packaging Semiconductor, Memory and Computing Division
Fan-Out Wafer and Panel Level Packaging Trends
At 3:45pm, September 8th
Fan-out wafer and panel level packaging has evolved from a low-end packaging technology into a high-performance and cost-effective integration platform. It can address some of the challenges of heterogeneous integration of different elements at package level. The technology can be used for various 2.5D and 3D multi-chip integrations, reducing system-level form factor while bigger dies with higher I/O density are being integrated. Simultaneously, FO package electrical performance and reliability are being improved. Consequently, big industry packaging players are placing huge investments in this technology. Fan-out packaging revenue for 2021 reached a notable $2.1B and it will grow at an 11% CAGR to reach around $4B in 2027. This grow will be mainly propelled by HD FO and UHD FO platforms, as fan-out will being increasingly adopted for applications like mobile APE, networking and HPC. Cost advantage via economy of scale is the strongest driving force for the adoption of FOPLP. So far, it has been adopted for low to mid-end applications like PMIC and APE. If the large-die trend continues, FOPLP will get more attractive for cost-yield reasons and the ability to scale heterogeneously will make it a promising packaging option for large-die partitioning and HPC applications. Even though FOPLP can offer cost advantages, the technical, financial and supply chain challenges are still not overcome. While FOWLP is already a mature technology, FOPLP is still in an early stage of development. The relentless requirement to achieve smaller feature sizes and the ambition towards larger panels due to cost reasons makes the yield harder to manage and will increase cost. Ultimately, if more FO packaging manufacturers implement FOPLP which is appealing for fabless companies and OEMs, then the supply chain will have to increase efficiency and make it a more flexible technology.
More information and registration: HERE
Technology & Market Analyst, Semiconductor Packaging
Gabriela Pereira is Technology & Market Analyst, Semiconductor Packaging at Yole Group.
Working within the Manufacturing & Global Supply Chain activities at Yole Group, Gabriela focuses on advanced packaging platforms, develops technology & market reports, and is engaged in dedicated custom projects.
Gabriela’s experience in the semiconductor field includes working at Amkor Technology, first for her master’s thesis and then as a R&D Engineer, where she collaborated on several package development projects.
Gabriela holds a master’s degree in metallurgical and materials engineering from the University of Porto, Portugal.