YOLE GROUP WILL BE PRESENT AS EXHIBITOR AT CHIPLET SUMMIT 2024
Chiplets improve chip yields and costs, but still provide the performance of a large monolithic chip. Designers can mix-and-match chiplets, use the process technologies best suited to particular functions, take advantage of chiplet IP, simplify moves to new process nodes, and avoid wafer waste and manufacturing defects. Chiplets are the key to producing the extremely high-density, high-performance chips required for today’s networking, storage, AI/ML, analytics, media processing, HPC, and virtual reality applications.
The Second Annual Chiplet Summit is the show chip designers can’t miss. Market players get the scoop on ways to make their chiplets run faster, scale better, use less power, and be more flexible. This unique event gives attendees a place to network with peers, ask questions of the experts, and talk to vendors offering a wide variety of products and services.
Meet Yole Group analysts and look through our latest market, technology, reverse engineering and reverse costing analysis with direct discussion with the team!
Interested in an onsite meeting with us? Send us your request at events@yolegroup.com
Yole Group will be also part of the program with a co-presentation:
Wednesday, February 7th
9am – 10am: Chiplet Markets Are Rising: Where and When?
Tom HACKENBERG,
Principal Analyst,
Computing
Ying-Wu LIU,
Technology & Cost Analyst,
Computing
ABSTRACT:
Chiplets are the approach all major chipmakers have adopted for smaller design nodes. However, their advantages depend on many factors including front-end wafer cost, silicon area required by overhead (such as interconnect and power distribution), disaggregation and integration costs, and more complex packaging and test processes. A new model simulates the cost differences between monolithic and chiplet approaches. It predicts which SoCs will benefit most from chiplets. Analysts can use the model to identify applications where chiplets offer the largest gains, and designers are most likely to turn to them.
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Ying-Wu Liu
Senior Technology & Cost Analyst, Computing
Ying-Wu Liu is Senior Technology & Cost Analyst, Computing at Yole Group.
Ying-Wu brings solid expertise in semiconductor technologies, with a specific focus on SoC, MCU, ICs, advanced nodes, and advanced packaging platforms. Her mission at Yole Group is to lead reverse engineering and cost analysis activities in the computing sector.
Leveraging extensive experience in physical and electrical device analysis, as well as hands-on knowledge in wafer manufacturing, Ying-Wu collaborates closely with internal and external laboratories to define and execute detailed teardown strategies. Her work supports the identification and analysis of manufacturing processes and technical choices implemented by IC makers. This enables a clear understanding of device architecture and its direct correlation with cost and technological innovation.
Prior to joining Yole Group, Ying-Wu held the position of Technical Support Manager at KEOLABS (France) and worked as an integration and R&D engineer in semiconductor foundries in Taiwan for nearly four years.
Ying-Wu holds a Master’s degree in Theoretical Physics from National Tsing Hua University (Taiwan) and a Master’s degree in Integration, Security & Trust in Embedded Systems from Grenoble INP – ESISAR (France).
Tom Hackenberg
Principal Technology & Market Analyst, Computing
Tom Hackenberg is Principal Technology & Market Analyst, Computing at Yole Group.
Tom is an industry leading expert reporting on markets for semiconductor processors including CPUs, MPUs, MCUs and DSPs, SoCs, GPUs and discrete accelerators, FPGAs, and configurable processors since 2006. Tom is also well-versed in related technology trends including AI and edge computing, IoT, heterogeneous processing, chiplets, as well as vertical markets like automotive, computing and telecommunications where processor trends play a significant role.
Tom has appeared as a presenter on these topics at associated events as the Chiplet Summit, OCP ODAS Workshop on Chiplets, Rosenblatt’s Age of AI Scaling, System-on-Chip Conference, Vision and AI Summit, Xilinx Adapt: Automotive: Anywhere, Yole Group’s events and as well as custom proprietary presentations.
He can also be found quoted or bylined in news and trade publications such as Cision, Computerworld, Design and Reuse, EE|Times & EE|Times Asia, Fierce Electronics, Insider, Semiconductor Engineering, VentureBeat, and more for expertise on the processor market.
Tom worked with market-leading processor suppliers developing both syndicated and custom research. He holds a BSEE/BSECE from the University of Texas at Austin specializing in processors and FPGAs.
