Tradeshows & Conferences

MiNaPAD – 2022

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MiNaPAD, the « Micro/Nano-Electronics Packaging & Assembly, Design and Manufacturing Forum » will be held in Grenoble, France, at the WTC congress center on june 23th-24th, 2022.

MiNaPAD is a 2 days conference with an exhibition. The objective of this event is to reinforce the design community (which constitutes the largest share of the semiconductor community in Europe) and the assembly and packaging community:

  • parallel technical sessions
  • an exhibition
  • additional  technical events

Grenoble – Europe’s conveniently located technology cluster for semiconductor research, design and manufacturing – easy access to Lyon (1 hour), Geneva (2 hours), Paris (3 hours by high speed train– TGV) airports

Yole Développement will participate in the following:

Stefan CHITORAGA photo

“Technology and Market Trends of High-End Performance Packaging – 2.5D & 3D”

On June 24th at 11:40am
By Stefan Chitoraga, Technology & Market Analyst at Yole Développement

“High-End Performance Packaging with its 2.5D & 3D solutions has become critical and effective for foundries and IDMs, increasing device performance and bandwidth, and reducing the gap between Si and substrate. OSATs are also following this trend, offering innovative advanced packaging solutions that help solve front-end challenges with the slowing of Moore’s Law, resulting in bigger dies to improve performance – fueled by the adoption of high-performance applications.

There is an increased implementation of end-system units in high-performance computing, cloud computing, networking, artificial intelligence, autonomous driving, personal computing, and gaming. At the same time, there are die power improvements at escalating cost associated with more advanced nodes scaling resulting with bigger and more complex dies. These trends had triggered semiconductor industry to strategize system-level scaling with high-end packaging solutions instead of purely scaling FE advanced nodes. In this context heterogeneous integration is a potential path forward to optimize the scaling cost by partitioning SoC chips and scale only those most critical circuit blocks. Therefore 2.5D and 3D heterogeneous integration technology with high interconnection density, high bandwidth, and high-power efficiency are required to achieve this.

Strong progress in R&D and production is driving advanced packaging technologies, such as TSV 3D Stacked Memory, 2.5D Interposers, UHD FO, Embedded Si Bridge and 3D SoC (Hybrid bonding), to the next level of IO density and functional integration, in high-end performance applications. 3D SoC – die to wafer and die to die hybrid bonding is viewed as the next technology breakthrough to achieve 10?m fine pitch. Regarded as a front-end packaging technology, this enables system-level high-end performance with denser 3D IC stacking of 3D DRAM, heterogenous integrated packages and packaged partitioned SoC dies. Leading suppliers, especially TSMC, YMTC, Samsung and Intel, are all targeting this by providing cutting-edge hybrid bonding solutions. This is perhaps the true contact point between the semiconductor and packaging worlds.

Is hybrid bonding technology the most suitable for the coming years? What are the driving markets, and which will be the killer application? Which players will lead the battle? From technology to market, an overview of innovations, applications, players & markets will be shared and debated to shed light on these questions and on 2.5D and 3D packaging impact on industry.

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