Stacking: the future for packaging technologies!

Register now

Stacking packaging yole semi 2019


FREE WEBCAST – January 22nd, 2019 at 5 PM CET – 8 AM PDT

TSV technology is entering a fierce battle with alternative stacking technologies from OSAT’s & foundries.

Share this webcast with your colleagues !

Not able to attend the webcast ? You can access the replay and the materials with the same registration link during one year.


Stacking technologies are becoming more and more famous thanks to the high performances, low consumption and footprint requirements in different applications and markets.

As for today the TSV and hybrid bonding are the 2 technologies used to stack dies in a wide range of applications (example: High performance computing and CMOS image sensor). OSAT’s and players like Samsung and Intel are developing their proper stacking technologies to replace TSV interposer. Technology like 3D SoC is also a contender to 2.5D.

The battle is ongoing and TSV will be very quickly challenged in certain markets as CIS, while it stills the dominant technology for HPC.

The webcast provides an overview of the markets/applications where stacking is and will be used. We will also evoke the trends and the opportunities of stacking technologies for different markets. 

Join us to discuss and debate on those topics, their status and future.

Mario Ibrahim Yole Développement


As a Technology & Market Analyst, Advanced Packaging, Mario Ibrahim is a member of the Semiconductor & Software division at Yole Développement (Yole). Mario is engaged in the development of technology & market reports as well as the production of custom consulting studies. He is also deeply involved in test activities business development within the division. Prior to Yole, Mario was engaged in test activities development on LEDs at Aledia. He was also in charge of several R&D advanced packaging programs. During his 5 years stay, he developed strong technical & managerial expertise in different semiconductor fields. Mario holds an Electronics Engineering Degree from Polytech’ Grenoble (France). He spent 3 apprenticeship years within Imaging Division of STMicroelectronics Grenoble, where he contributed to the test benches park automation within the test & validation team.

Related report

2.5D / 3D wafer level integration technology & market updates 2019

Discover more Advanced Packaging related reports here

Do you have an account?

Sign in to your account to access your services