The Battlefields of Fan-Out Packaging

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All key players with different FO technologies are facing an unavoidable battle of cost and performance trade-off between panel-level vs. wafer-level.

In 2019, key players from all different business models like OSATs, foundries and IDMs have Fan-Out packaging solutions in the market. Fan-out packaging technology is not only a bridge to chip-package interaction (CPI) mismatch in pitch size, but is also a viable solution for heterogeneous integration of functionalities, now potentially used for mmWave 5G and Cloud data server applications.

Fan-out packaging total market value is expected to grow at 19% CAGR from 2019 to 2024, reaching a market size of $3.8B. Fan-out success is evidently defined by the well-established “core” standard FO market and the startling market penetration of high-density FO (HDFO), which brought Fan-Out Packaging into a whole new level of spotlight.

FOWLP players like Amkor Portugal (NANIUM, S. A.) and JCET Group (STATS ChipPAC) used to have almost 80% market share prior to 2016. Since 2016 after Apple’s adoption of TSMC’s InFO for APE in iPhone 7 and beyond, new players like SEMCO, PTI, SPIL, Nepes, ASE/Deca are all entering FO market with different strategies and technologies.

Join Yole Développement and System Plus Consulting in this webcast to gain insights on the different levels of battles that are unfolding in, arguably, one of the most exciting advanced packaging platforms – Fan-Out Packaging.

Related reports:

Fan-Out Packaging: Technologies and Market Trends 2019
Samsung and PTI, with panel-level packaging, have entered the Fan-Out battlefield.

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