High-End Performance Packaging 2023

Key Features

The High-end Packaging market was worth $2.2B in 2022 and is projected to reach over $16B by 2028, with a CAGR2022-2028 of 40%. Breaking it down further into its end-markets, the biggest market in High-end Performance Packaging is ‘Telecom & Infrastructure’, with more than 60% of the market revenue in 2022. But it should be surpassed by ‘Mobile & Consumer’ market by 2027. Equally important is that the fastest end-market growth in High-end Packaging is coming from ‘Mobile & Consumer’ and ‘Automotive & Mobility’, at 50% and 32% CAGR, respectively. 3D Stack memories - HBM, 3DS & 3D NAND are the biggest contributors, representing more than 70% combined market share by 2028. The top four fastest-growing platforms are 3D SoC, Active Si Interposer, embedded Si bridge & 3D NAND stack. ​

What’s new? ​

• New technology platforms added;​
• New assumptions;​
• Forecast updated

Product objectives

• Identify and describe which technologies can be classified as ‘High-end Performance Packaging’​
• Define High-end Performance Packaging​
• Analyze key market drivers, benefits, and challenges of High-end Performance Packaging, by application ​
• Describe the different existing technologies, their trends and roadmaps​
• Consider the supply chain and High-end Performance Packaging landscape​
• Update the business status of High-end Performance Packaging technology markets​
• Provide a market forecast for the coming years, and estimate future trends

Table of contents ​

Glossary​

About the authors ​

Objectives of this report ​

Key features of this report ​

Companies cited ​

Who should be interested in this report? ​

What we got right, what we got wrong                                      ​

Methodology and definition ​

3-Page summary ​

Executive summary ​

Introduction ​

• Moore’s law​
• Performance Demand in Semiconductor ​
• High-end performance packaging definition​
• Scope of the report​
• Type of high-end performance packaging​

Market forecasts ​

• Package ASP update split by technology ​
• Market revenues - Split by end-market and technology​
• Market units - Split by end-market and technology ​
• Market size split by technology ​
  • 3D SoC ​
  • 3D Stacked memory​
  • RDL Interposer​
  • 2.5D Interposer​
  • Embedded Si bridge​
• Chapter conclusion

Accretech, Adeia, ADI, Alibaba group, Amazon, AMD, Amkor, Applied Materials, ARM, ASE, ASMPT, Atmel, Atos, Baidu, Besi, Biren Technology, Blue Ocean Smart System, Brewer Science, Broadcom, BroadPak, Cambricon, Canon, Casmeit, CEA-Leti, Cerebras, Corning, Cray, Cyber Optics, Cypress, Disco, Dupont, Ebara, Eliyan, Empyrean, Entegris, EVG, Facebook, Foxconn, Fraunhofer IZM, Freescale, Fujitsu, Global Foundries, Gloway,  Graphcore, GUC Glink, Hanni, HD Microsystems, Hi-Silicon, HLMC, Hua Tian, Huawei, Ibiden, IBM, IME, IMEC, Integra, Intel, Infineon, Invensas, ITRI, JCET, Juniper Networks, Kioxia, KLA, Kyocera, Lam Research, Lapis Technology, LB Semicon, Marvell, Mediatek, Meta, Micron, Microsoft, Micross Components, Mitsubishi,  NEC, Nepes, Nhanced Semiconductors, Nokia, Nvidia, Ommi Vision, onsemi, ONTOS TT, Oracle, Panasonic, Plasma Therm, PRC Georgia Tech, Protean Tecs, PTI, PVA Tepla, Qorvo, Qualcomm, Quavo, Raytheon Technologies, Renesas, RISC-V, Rohm, Samsung, Sandia National Laboratories, Sanyo, Semco, Semsysco, Set, Sharp, Shinetsu, Shinko, Showa Denko, Siemens, Silicon Box, SK Hynix, Skywater, SMIC, Sony, SPIL, SPTS, ST Microelectronic, Sunlune, Surfx Technologies, TI, Suss Microtec, Synopsys, TEL, Tencent, Tesla, Tezzaron Semiconductor, TFME, Tokyo Electron, Toshiba, Tower Semiconductor, Nanya, TSMC, UMC, Unimicron, Unity SC, Ventana, Western Digital, Xilinx, Yibu Semi, YMTC and more.

High-End Performance Packaging is experiencing a whopping growth​

The high-end packaging market was worth $2.2B in 2022 and is projected to reach over $16B by 2028, with a CAGR2022-2028 of 40%. Breaking it down further into its end-markets, the biggest end-market in high-end performance packaging is ‘telecom & infrastructure’, which held more than 60% of total market revenue in 2022. However, it should be surpassed by the ‘mobile & consumer’ end-market by 2027. Equally important is that the fastest end-market growth in high-end packaging is coming from ‘mobile & consumer’ and ‘automotive & mobility’, at 50% and 32% CAGR, respectively. In terms of package units, high-end packaging is projected to experience a 43% CAGR2022-2028, from 511M units in 2022 to 4,379M by 2028. This huge growth is explained by the fact that in the case of high-end package, the demand is increasing in a very healthy way and the ASPs are very high compared to less advanced packaging, since there is a transition of the value from front-end business to back-end business forced by 2.5D & 3D platforms. ​

3D stack memories – HBM, 3DS, and 3D NAND – are the biggest contributors, representing more than 70% combined market share by 2028. The top four fastest-growing platforms are 3D SoC, active Si interposer, embedded Si bridge, and 3D NAND stack. 

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​High-end performance packaging is becoming more complex, adopting new solutions​

The main technology trend for all high-end performance packaging platforms consists of reducing interconnection pitch, no matter the type. This relates to TSVs, TMVs, microbumps, and even hybrid bonding, which is already the most aggressive solution. On top of this, via-diameter and wafer thickness are expected to be lowered. This technology evolution is necessary for keeping the integration of more complex monolithic dies on one hand, and of chiplets on the other hand, to support faster data processing and transmission while ensuring less power consumption and loss and allowing higher density integration and bandwidth for future generations. ​

Chiplet and heterogeneous integration is another important trend fueling the adoption of HEP packaging, as there are already products using this approach on the market. Examples are Sapphire Rapids using EMIB; Ponte Vecchio using Co-EMIB; and Meteor Lake using Foveros from Intel. Also, Amazon used Intel’s EMIB technology for its Graviton3. AMD is another important player adopting this technology approach in products like Ryzen and Epyc, starting with the 3rd generation, as well as duplicated die in its MI250 thanks to a package using mold interposer with embedded silicon bridges in mold compound. Silicon bridges embedded in mold compound together with mold interposer were also used for Apple’s M1 Ultra to allow die duplication. Tesla’s Dojo D1 uses an InFO_SoW solution from TSMC to interconnect 25 chiplets in the same package. Biren uses TSMC’s CoWoS solution to interconnect two chiplet dies in its BR100. More packages incorporating partitioned or duplicated dies are expected to hit the market in the coming year, as has been clearly announced by important players such as Intel, AMD, Nvidia, and others.​

Co-packaged pptics (CPO) is an advanced heterogeneous integration of optics and silicon on a single packaged substrate, aimed at addressing next-generation bandwidth and power challenges. Even if its adoption does not happen soon, this approach will represent an important technological improvement. In fact, ASE already announced in its roadmap the capability to provide services for this kind of package configuration.​

Hybrid bonding is today’s hot topic, as the technology is getting more and more popular via its W2W solutions for 3D NAND stack memory and CIS, as well as for logic-to-logic products like Graphcore’s BOW IPU. In 2022, AMD commercialized its V-Cache technology with its Ryzen and Epyc products being first-of-their-kind to use a D2W approach for SRAM-to-logic chiplet interconnection thanks to TSMC’s 3DFabric. Hybrid bonding should get more traction, as a collective D2W approach is expected to be used for stacking DRAMs in HBM3+ generation. Moreover, new players using this approach will penetrate the market. The next step will be to use the D2D approach to support chiplet and heterogeneous integration trend.​

The 3D technology trend is to adopt more HB for stacking in the coming years. Memory players will use more W2W, and then collective D2W HB. Logic players will use more D2W HB, which allows more flexibility for heterogeneous integration as well.  The W2W approach will follow, getting more popular as well. The classical approach combining TSV with µbumps for HBM and 3DS will continue dominating as a solution, while the future will have die-to-interposer HB options.​

The general trend is to have more 2.5D platforms combined with 3D platforms in the same package. Therefore, we expect future packages to integrate chiplets using 3D SoC, 2.5 interposer, embedded silicon bridges, and co-packaged optics in the same package. New 2.5D & 3D packaging platforms will hit the market later, making HEP packaging much more complex.

The barrier to entry into the HEPP supply chain is increasingly high​

The high-end packaging supply chain is evolving towards long-term viability with sustainable business cases, as some players propose HEP packaging solutions – without which some products and performances would not even be achievable in the market presently. That’s because high-end package platforms are moving closer towards front-end manufacturing. Obviously, there is a need for front-end capability to produce silicon interposers, silicon bridges, 3D stacked memories, and 3D SoCs. Therefore, TSMC, Intel, and Samsung are top players driving innovation for HEP packaging. TSMC is present with its 3DFabric, leveraging CoWoS, InFO, and 3D SoIC solutions. Intel is using its Foveros, EMIB, and Co-EMIB products, and later on Foveros Direct & Omni. Samsung is the pioneer in HBM and 3DS memory and is providing I-CubeS, H-Cube, and later R-Cube & X-Cube too.​

Currently, companies with different business models (foundry, IDM, and OSAT) are competing in the same high-end packaging market space.  However, the number of players that can achieve high levels of packaging quality is limited because the level of complexity for high-end, or in some cases front-end manufacturing and integration, has made it difficult for players to penetrate the market. In 2022, YMTC, Samsung, SK hynix, and Micron dominated the market for revenue market share, as 3D stack memories are the main contributor to the HEP packaging business. ​

The barrier to entry in the high-end packaging supply chain is hence increasingly high, especially with the adoption of hybrid bonding, making it impossible for OSATs to follow. Big players such as Intel, TSMC, and Samsung have successfully tapped into advanced packaging market growth and achieved faster time-to-market than OSATs for high-end performance packaging. This strategy poses an indirect yet formidable threat to OSATs.​

Within high-end packaging, OSATs’ business is being cannibalized by foundries and IDMs. Moving forward, fabless may become attracted by the prospect of cutting-edge turnkey services, such as the latest silicon node manufacturing technology coupled with advanced packaging. However, top OSATs like ASE, SPIL, Amkor, JCET, TF, and Huatian are managing to keep pace with the leading-edge packaging businesses, focusing on 2.5D solutions like organic interposers and embedded silicon bridges in mold compound. This is a very good alternative to the missing possibility of accessing the market of hybrid bonding. Even if OSATs can’t produce HEP packaging solutions close to FE manufacturing, they are omnipresent for the final package assembly & test.  ​

OSAT and substrate suppliers can potentially command large packaging value at system level, but they are not equipped financially or technically to manufacture and manage FE dies on their own with their current equipment and materials know-how. Hence, they can either turn to fabless, foundry, or IDM for partnership, or seek M&A opportunities directly.​

There have been many investment and capacity expansion announcements these last two years, mainly happening in China. More Chinese players are expected to use or provide HEP packaging solutions, participating in business growth. The technology providers are still the same key players, with more package options offered in 2.5D and 3D technologies.

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