Intel Foveros 3D Packaging Technology

As feature scaling hits the limits of physics, the semiconductor industry is already researching for “more-than-Moore” technology enablers. In this area, multi-die packages are essential to integrate more functions into a small form factor, whatever is the lithographic technology node, be it conventional integrated circuits (ICs) at 7nm, or Radio Frequency (RF) ICs at 28 nm. All this must be at low cost and in a short time to market. From this perspective, Intel has developed several interconnect technologies to enable heterogenous integration using chiplets. An early glimpse of the technology enablers was seen in 2018 on an Intel processor, then called Embedded Multi-die interconnect Bridge (EMiB). Today, Intel shows another way to interconnect dies in processor using an active interposer and Foveros technology.

Foveros allows 3D Face-to-Face (F-F) stacking for integration of different types of devices on an active interposer using Through Silicon Vias (TSVs). The interposer is used as a bridge for the different chiplets. However it also comprises low-power components such as input/output (I/O) connections and power delivery with high performance logic.

The Intel Core i5-L16G7 analyzed in this report features Intel’s hybrid packaging technology. This technology relies on Foveros F-F die stacking and Package-on-Package (PoP) configuration. The design aims to integrate 10 nm computing die with SK Hynix LPDDR4 DRAM in a PoP architecture in a single package. This lowers power consumption and increases core performance while reducing the form factor and z-height to fit ultra-mobile applications. In the structure, the 10 nm computing die is directly connected to a 22 nm Interposer using Foveros F2F technology and via-middle TSVs. That allows easy power transfer to the processor chip.

This report constitutes an exhaustive analysis of the Intel Core i5-L16G7 processor. This report includes a full investigation of Intel’s hybrid packaging technology. It features a detailed study of the 3D package including the processor die, Foveros features and interposer die analysis and cross-sections. The report also integrates the physical analysis of the LPDDR4X DRAM dies integrated in the package. Finally, it contains a complete cost analysis and a selling price estimation of the component and a physical comparison with TSMC’s Chip-on-Wafer-on-Substrate (CoWoS) technology.

Overview/ Introduction 

Company Profile: Intel

Samsung Galaxy S Book Teardown 

Physical Analysis 

• Board Analysis
  • Board overview: Heatsink dimensions, PCB substrate
• Package Analysis
  • Package on package views
  • Package on package opening and cross section
• DRAM Memory Analysis
  • Package view and dimensions
  • Package and die cross section
• Processor Analysis
  • Package overview and cross-section: Interposer, PCB substrate
  • Interposer and processor die analysis

Physical Analysis Comparison

Intel’s Foveros Technology vs. TSMC’s CoWoS

Manufacturing Process

• DRAM Front-End Process and Fabrication Unit
• Interposer and Processor Front-End Process and Fabrication Unit
• Processor Packaging Process Flow
• Package on Package Assembly

Cost Analysis

• Overview of the Cost Analysis
• DRAM Memory Cost Analysis
• Processor Cost Analysis
• Interposer Cost Analysis
  • Bumping back-end cost and cost per step
  • Wafer and die cost
  • Packaging cost and cost per step
  • Packaging wafer and component cost
• Component Cost Analysis
  • Package on package cost and cost per step
  • Final test and component cost

Estimated Price Analysis

Reverse costing with:

• Detailed photos
• Precise measurements
• Material analysis
• Manufacturing process flow
• Supply-chain evaluation
• Manufacturing cost analysis
• Estimated sales price
• Comparison with TSMC’s CoWoS