Intel’s Embedded Multi-Die Interconnect Bridge (EMIB)

Overview/Introduction

Company Profile

Market Analysis

Physical Analysis

• Intel NUC8i7HVK Teardown
• Processor Package
  • Views, dimensions and overview
  • Die sizesBoard cross-section
  • Package disassembly and cross-section: metal frame, laminate substrate, silicon bridge
• GPU die
  • Views, dimensions and marking
  • Microbumps
  • Silicon bridge to GPU cross-section
• Driver and DRAM Die
  • Views, dimensions and marking
  • Microbumps and TSVs
  • HBM2 stack cross-section
  • Silicon bridge to HBM2 cross-section
• Silicon Bridge Die
  • View, dimensions and marking
  • Microbumps
  • Silicon bridge cross-section: Substrate, metal layers, process
• Comparison with NVIDIA Tesla P100 and AMD Radeon Fury X

Manufacturing Process

• IGBT Front-End Process and Fabrication Unit
• Diode Die Front-End Process and Fabrication Unit
• Final Test and Packaging Fabrication Unit

Manufacturing Process

• Global Overview
• HBM2 Stack Process Flow
• Silicon Bridge Process Flow
• EMIB Process Flow IGBT Front-End Process and Fabrication Unit
• Diode Die Front-End Process and Fabrication Unit
• Final Test and Packaging Fabrication Unit

Cost Analysis

• Overview of the Cost Analysis
• Yield Hypotheses
• GPU Front-End and Die Cost
• Silicon Bridge Wafer and Die Cost
• DRAM Front-End Cost
  • TSV manufacturing cost
  • Microbumping manufacturing cost
• DRAM Die Cost
• Logic Die Cost
• HBM2 Stack Cost
• EMIB Assembly Manufacturing Cost
• Final Component Cost

Estimated Price Analysis

In the last few years, as the central and graphics processing unit (CPU and GPU) technology has advanced, the need for high DRAM memory bandwidth has led to an increased focus on high bandwidth on-package links. And so, localized high-density interconnects devices between two or more dies has been investigated to provide high bandwidth signaling in order to open up new opportunities for heterogeneous on-package integration. The typical proposed devices are interposers in glass, organic or silicon substrates. Intel has developed its own approach called an Embedded Multi-die Interconnect Bridge (EMIB), which offers simpler integration.

We have analyzed the Intel Core i7-8809G, which is the eight generation of Intel core i7 processor. The processor features a CPU, a discrete GPU and second generation high bandwidth memory (HBM2) on the same package. The GPU has a 4GB high bandwidth cache assembled from one 4-Hi HBM2 stack of four DRAM dies, giving almost 200GB/s of bandwidth.

Whereas NVIDIA and AMD both use interposers with via-middle TSVs, the Intel product uses EMIB technology. This consists of a silicon bridge buried in the printed circuit board (PCB) substrate, making the interconnection between the HBM2 stack and the GPU. The approach has some inherent advantages, such as the ability to implement high-density interconnect without requiring TSVs and to support the integration of many large dies in a large area.

Focusing on the GPU and HBM integration, the report shows that in a small 29mm x 19mm area 12-layer flip-chip ball grid array (fcBGA) package, both components use under 700mm² of silicon, an impressive silicon-to-package ratio.

This report includes a complete physical analysis of the packaging process, with details of all technical choices regarding processes, equipment and materials. Also, the complete manufacturing supply chain is described, and manufacturing costs are calculated.

The report compares the Intel solution with AMD’s Radeon Vega Frontier and NVIDIA’s Tesla P100, highlighting the integration choices made by all companies.

REVERSE COSTING WITH

• Detailed photos and cross-sections
• Precise measurements
• Material analysis
• Manufacturing process flow
• Supply chain evaluation
• Manufacturing cost analysis
• Estimated sales price
• Physical comparison with NVIDIA Tesla and TSMC CoWoS, and AMD Radeon Vega and SPIL CoW