Technology, Process and Cost
MediaTek Dimensity 9000 SoC
By Yole SystemPlus —
Full analysis of MediaTek’s first 4nm SoC in the Xiaomi Redmi K50 Pro. The world’s first chip manufactured with TSMC’s 4nm FinFET process.
Overview
- Executive Summary
- Product Specification
- Reverse Costing Methodology
- Glossary
Company Profile
- Company Profile
- MediaTek Dimensity Series
- Market Analysis
Physical Analysis
- Smartphone Dismantle
- Packaging Analysis
- DRAM Die
- SoC Die
- FEOL (TEM Analysis)
Manufacturing Process Flow Analysis
- Global Overview
- SoC Die Front-End Process
- SoC Die Front-End Wafer Fabrication Unit
- Advanced PoP BGA packaging process
Cost Analysis
- Cost Summary
- Yields Explanation & Hypotheses
- Soc Die Front-End Wafer Cost
- SoC Die Cost
- Packaging Cost
- Component Cost
Selling Price
- Definitions of Price
- Manufacturer Financials
- Estimated Selling Price
Feedback
Related Products
About Yole Group
This full reverse costing study was conducted to provide insight regarding the technology data, manufacturing cost, and selling price of the MediaTek Dimensity 9000 system-on-chip (SoC).
As one of the strongest fabless chip designers in the world, MediaTek has been developing smart technology for mobile computing, networking, smart home, IoT, ASIC, and power IC. In 2020, MediaTek launched the Dimensity SoC series as an ultra-efficient chip for 5G smartphones. In 2022 Q1, Dimensity 9000 SoC was published. This innovative product is the first chip manufactured by the world’s most advanced TSMC 4nm technology. The SoC is equipped with an ultra-core of Arm Cotex-X2 at 3.05 GHz, three Arm Cortex-A710 up to 2.85 GHz, four Arm Cortex-A510, and the proprietary HyperEngine 5.0 to top up the gaming experience and reduce the GPU load. To boost the AI performance, the chip includes MediaTek’s updated APU 590, which is four times more efficient than the previous generation. According to MediaTek, Dimensity 9000 integrates the world’s first R16 UL (Release 16 Uplink) Enhancement as its 5G modem and features the leading Wi-Fi 6 and Bluetooth 5.3.
The MediaTek Dimensity 9000 SoC contains a SRAM cache in the die and includes an external LPDDR5X DRAM with packaging. The advanced ball-grid-array packaging technology is used for integrating the SoC die with the upper and bottom substrate. Then, the DRAM package is stacked on the SoC die package with PoP (package-on-package) technology.
To reveal all the details of the Dimensity 9000, this report features multiple analyses. One is a front-end construction analysis to reveal the key features of the TSMC 4nm process, and another is a back-end construction analysis for the packaging structure. This report also includes a detailed study of the SoC die and its cross-sections. In addition to a complete analysis by using SEM cross-sections, material analyses, and delayering, we show a high-resolution TEM cross-section of TSMC’s 4nm technology. A CT-scan (3D X-ray) is also provided to reveal the layout structure of the SoC die package. Moreover, the floorplan of the SoC die is presented in order to provide a clear view of IP blocks. Lastly, this report furnishes a complete cost analysis and a selling price estimation of the MediaTek Dimensity 9000 die.
- MediaTek
- TSMC
Key Features
- Detailed photos
- Precise measurements
- Front-end structural analysis with TEM
- Comparison with TSMC 5nm and 4nm front-end-of-line, in TEM view
- Back-end structural analysis with CT scan
- Floorplan (second version)
- Materials analysis
- Manufacturing process flow
- Supply chain evaluation
- Manufacturing cost analysis
What's new
The world’s first TSMC 4 nm SoC, designed by MediaTek
Available on our Yole Group All-Inclusive Computing Package