Technology, Process and Cost
Samsung 176 layer 3D NAND Memory
By Yole SystemPlus —
Samsung’s seventh generation V-NAND using Cell-over-Peripheral architecture and double deck implementation
SPR23719
Overview
- Executive Summary
- Reverse Costing Methodology
- Glossary
Company Profile
- Samsung Financial result & location
- NAND Evolution
- Samsung 990 PRO SSD
- Market Dynamics
Physical Analysis
- Summary of the physical analysis
- SSD Disassembly
- Packaging
- Memory Die
Physical Comparison
Manufacturing Process Flow Analysis
- Global Overview
- Memory Die Front-End Process
- Memory Die Front-End Wafer Fabrication Unit
- Process Steps
Cost Analysis
- Cost Summary
- Yields Explanation & Hypotheses
- Die Front-End Wafer Cost
- Die Cost
- Packaging Cost
- Component Cost
Cost Comparison
Selling Price
- Estimated Selling Price
Feedbacks
Related Products
About Yole Group
Key Features
- Detailed photos
- Precise measurements
- Materials analysis
- Physical comparison of Generations 6 and 7
- Manufacturing cost analysis
- Supply chain evaluation
- Manufacturing cost analysis
- Cost estimation
- Cost comparison
What's new
- New architecture/design
- CMOS/peripheral logic circuit placement
- Double deck process flow
- Chips with double capacity
- Density improvement
- Samsung
Samsung maintained a sizeable lead in the NAND memory market throughout 2022, with an average share of 34%. NAND demand has remained extremely weak through the end of 2022. Samsung introduced its 990 PRO solid-state drive (SSD) in the second half of 2022 based on the 7th generation V-NAND using 176-layer memory chips.
Samsung, like its NAND memory competitors, continues to stack numerous wordlines vertically. This aims to provide greater capacity, faster speeds, and decreased power usage. In the latest V-7 generation, the total gate count is increased by more than 40% compared to the previous generation V-6 NAND. To stack up to 191 gates, Samsung finally introduced multiple decks and reduced wordline pitch to ease the high aspect ratio etching. With this new design it supplied its customers with 512 gigabit dies, double the die capacity of its previous generation chips without a significant change in chip area. For several generations, Samsung’s memory architecture has integrated peripheral circuits around the sides of the NAND chip. In this new memory chip it has redesigned the architecture to use Cell-over-Peripheral (COP) implementation for the first time. This allows Samsung to increase its memory density by manufacturing the NAND array on top of the CMOS.
This report presents a detailed study of Samsung’s latest 176-layer V-NAND using triple-level NAND memory cells. High-resolution scanning electron microscope (SEM) images showcase multiple dies that are vertically stacked in a ball grid array package. The die cross-sections reveal the NAND array cells on the peripheral circuit and the multiple decks. The report provides details on the major fabrication steps and process flow. The cost estimation includes both front end and back-end cost and Samsung’s one terabyte (1TB) component cost.
Finally, this report features a comparison of the Samsung’s previous generation V-6 NAND using 128 layers. It physically compares the package and die, and compares die density, wafer cost, and die cost. This comparison will identify the differences in the physical features between Samsung’s 128-layer 3D NAND and its latest 176-layer 3D NAND.
