Technology, Process and Cost
SK Hynix 176-layer 3D NAND
By Yole SystemPlus —
SK hynix’s next-generation triple-level cell NAND memory using periphery under-cell design and charge trap flash.
- SK hynix
- Detailed photos
- Precise measurements
- Cross-section SEM images
- Materials analysis
- Manufacturing process flow
- Supply chain evaluation
- Manufacturing cost analysis
- Comparison with 128-layer NAND
- Added / increased wordline layers from 128 layers to 176 layers
- Reduced wordline pitch
- Higher density
- Increased wafer productivity in terms of memory (GB/wafer)
- New / smaller CMOS process technology
- Flash memory added on die
- Executive Summary
- Product Specification
- Reverse Costing Methodology
- Company Profile
- SK hynix
- Market Analysis
- Board Teardown
- Packaging Analysis (dimensions, X-Ray, cross section , opening)
- NAND Die Analysis (dimensions, cross section , delayering, process)
Manufacturing Process Flow Analysis
- Global Overview
- NAND Die Front-End Process
- NAND Die Front-End Wafer Fabrication Unit
- Final Test and Packaging Process
- Cost Summary
- Yields Explanation & Hypotheses
- NAND Die Front-End Wafer Cost
- NAND Die Cost
- Packaging Cost
- Component Cost
- Definitions of Price
- Manufacturer Financials
- Estimated Selling Price
About Yole Group
SK hynix’s NAND memory revenue increased by 35% between fiscal years 2020 and 2021, reaching $9 billion in FY 2021. The company’s NAND market share was estimated at 14% in 2021. In Q2 2022, SK hynix introduced the Platinum P41 SSD, using its 6th-generation NAND memory with 176-layer triple-level cell NAND, targeting personal computers.
Different approaches have been used to scale down the physical dimension of memory cells. Lately, scaling in the z-direction has been adopted and optimized by several NAND memory manufacturers. This involves increasing the number of wordlines with each generation. SK hynix increased wordline count by 37% compared to its previous generation, resulting in higher bit productivity. By using 176 wordlines, bit density is estimated to be 10.9Gb/mm². NAND memory dies of 512Gb with 28% smaller die area compared to the previous generation have been produced, resulting in an increased number of dies per wafer compared to the previous 128-layer NAND memory. A combination of periphery under-cell architecture and the adoption of a smaller CMOS technology node has boosted memory performance, contributing to superior read/write speeds.
16 NAND memory dies have been used to build 1TB NAND memory component in a single package. This report unveils SK hynix’s innovative solutions to reduce the high aspect ratio etch, which is a source of defects in 3D NAND manufacturing. The cross-section uncovers the use of double-stack architecture, reduction of wordlines, and the cell interlayer material thickness.
To reveal all the details of SK hynix’s next-generation 3D NAND using 176 wordlines, this report features several analyses. These include a front-end construction analysis that reveals the key features of the wordline stack and the patterning technology used in the process. Also, a back-end construction analysis offers details on the packaging structure. Moreover, this report includes detailed, high-resolution SEM images of the die cross-section. The SEM images are complimented by EDX analysis to determine the various materials used in the manufacturing process of the NAND memory. Lastly, this report furnishes a complete cost analysis and gross margin estimation. Some slides contain a comparison analysis between SK hynix’s 126-layer NAND memory and the 176-layer NAND memory.
Do you have an account?
Sign in to your account to access your services