YMTC’s 3D-NAND Flash Memory

Overview/Introduction

• Executive Summary
• Reverse Costing Methodology

Company Profile 

Market Analysis                                                                                                   

• NAND Flash Market Revenue
• NAND Production
• NAND Bit Demand

Physical Analysis

• Summary of the Physical Analysis
• Physical Analysis Methodology
• Gloway SSD Teardown
• Package
  • Package views and dimensions
• Memory Die
  • View, dimensions and marking
  • Cross-section
  • Contacts and metallization
• YMTC 3D NAND Patents

Comparison: 64 Layer YMTC vs 64 Layer Samsung/Kioxia/Micron

• Die, Process, Cross Section and Density Comparison
  • Die view and dimensions
  • Die cross section
  • Die delayering and main blocks
  • Die process characteristic

Manufacturing Process Flow

• Overview
• YMTC Memory Array Wafer Fab Unit
• YMTC CMOS Wafer Fab Unit
• YMTC Memory Process Flow

Cost Analysis

• Summary of the Cost Analysis
• Yield Explanations and Hypotheses
• Wafer Front End Cost
  • CMOS wafer front-end cost
  • NAND array wafer front end cost
  • Bonding front end cost
  • Memory front-end cost per process step
• Process Steps
• Component
  • Memory wafer and die cost
  • Back-end: Final test cost
  • YMTC 64-layer NAND memory component cost

Estimated Price Analysis

Reverse costing with:

• Detailed photos
• Precise measurements
• Materials analysis
• Manufacturing process flow
• Supply chain evaluation
• Manufacturing cost analysis
• Estimated sales price

NAND market revenue improved in the first quarter of 2020 due to the global lockdown, triggered by the COVID-19 pandemic compared to the previous quarter in 2019. Stronger storage demand was driven by increased remote work and online learning, which created a sudden demand for datacenter storage and PC solid state drives. This transition increased sales of NAND Flash memory. Yangtze Memory Technologies Co (YMTC) is expected to up pick a significant share of NAND market revenue.

YMTC launched the new 3D NAND Xtacking architecture that uses two wafers for its 64-layer 3D NAND memory instead of a single wafer used in conventional 3D NAND memories. The CMOS periphery and the NAND array wafer are manufactured separately. The wafers are connected by vertical interconnection. The bonding technique needs a high level of accuracy and alignment precision to perfectly join the metal layers from different wafers. This Xtacking process allows YMTC to increase its die density.

YMTC’s memory enters the NAND flash market as a solution to cater for higher I/O (Input/Output) speed because of the use of advanced CMOS that can be manufactured on a different wafer from the NAND array.  This memory provides the combination of high speed and large density characteristics.

Based on complete teardown analysis of the 3D NAND memory, this report will provide the fabrication steps of YMTC’s latest 64-layer NAND dies, the physical analysis will reveal the Xtacking architecture adopted by YMTC. A complete physical analysis will determine the die density, including the manufacturing process and cost estimation. The report also includes the impact of using two wafers on the NAND density and total manufacturing cost.

The manufacturing cost results are used to determine the cost per Gb for YMTC’s 3D NAND memory.

Finally, this report features a technical comparison of YMTC’s 64-layer NAND with the other 64-layer NAND memories from main NAND manufacturers like Samsung, Kioxia and Micron. This helps to compare the YMTC cell features and note the similarities and differences from other 64-layer NAND.