Webcasts
ANALYST THURSDAY 2024 : EXTENDING MOORE’S LAW THROUGH HIGH-END PACKAGING AND ADVANCED IC SUBSTRATES THAT ENABLE A PATHWAY FOR THE AI GENERATION
Register nowBy 2029, High-End Packaging is poised to hit $16.7B, fueling Generative AI expansion through chiplet and heterogeneous integration.
The advanced packaging market is set up to grow at a healthy pace, strongly driven by the megatrends of HPC, generative AI, high-end laptops and workstations, and autonomous driving. Considering all packaging platforms, the 2.5D/3D type of interconnect is the one growing at the fastest rate. The high-end performance packaging market is propelled by the massive growth of data center AI chips, the need for more computing power, bandwidth, speed, and high-end memory, and lower power consumption. As Moore’s Law is decelerating and die cost is growing exponentially, heterogeneous integration and chiplet adoption are gaining interest to support functionality, faster time to market, and compensate for exponentially increasing front-end costs. 2.5D interposers and 3D stacking solutions are the key enabling packaging technologies for generative AI accelerators, GPUs, CPUs, MCUs, and other high-end ASICS. Wafer-to-wafer and die-to-wafer hybrid bonding approaches are hot topics regarding technology breakthroughs as they allow a 10μm to 1µm fine pitch and possibly less. This enables denser 3D IC stacking of logic or memory dies, an interconnection of partitioned SoC dies, and heterogeneously integrated packages.
Advanced IC substrates are necessary to ensure the package connection to the system PCB, and they represent the silent workhorse in the generative AI hardware supply chain. The advanced IC substrate industry is focused on satisfying the increasing requirements of high-end applications, such as thermal management, form factor, power delivery, and signal routing. Industry giants, including TSMC, Intel, and Samsung, and top OSATs like ASE, Amkor, and JCET, are strongly investing in high-end advanced packaging capacity with a strong focus on AI-related technologies to answer the increasing industry demand.
Don’t miss this opportunity to gain valuable insights and stay informed about the evolution of the advanced packaging market and technology trends, as well as the top players from the supply chain.
The webinar will highlight:
- Global overview of the high-end performance packaging market versus the total advanced packaging market.
- High-end performance packaging market forecast and market drivers with a focus on generative AI applications.
- Overview of the high-end packaging technology trends, including hybrid bonding, chiplets, Si photonics & CPO, and FOPLP
- Summary of commercialized products with an emphasis on a few recent product teardowns: Nvidia H100 AI GPU and AMD 3D V-Cache
- Analysis of the advanced IC substrate market trends and drivers. Why are IC substrates critical for generative AI?
- Focus on the adoption of glass core substrates. When will the technology take off? What challenges must still be overcome?
- Overview of the high-end packaging supply chain, including package and substrate suppliers.
Leading semiconductor giants embrace chiplets and hybrid bonding, revolutionizing advanced packaging for enhanced performance and cost efficiency.
Read more…
Vishal Saroha
Technology & Market Analyst, Semiconductor Equipment
Vishal Saroha is Technology & Market Analyst, Semiconductor Equipment at Yole Group.
Based in Dresden (Germany), he focuses on developing technology and market products and custom consulting projects in the manufacturing and global supply chain domain.
Prior to Yole Group, Vishal worked at GlobalFoundries, Dresden, first as an Integration & Yield Engineer and then as Sr. Engineer - Integration Engineering, where he was the owner of device and SRAM targeting-related activities on their 22FDX technology. Previously, he also had experience at imec (Belgium), where he worked on issues related to 3DIC packaging and device reliability.
Vishal holds a master's in nanotechnology from Katholieke Universiteit Leuven (Belgium) and a bachelor's in physics from the University of Delhi (India).
Rayane Mazari
Technology & Cost Analyst, Semiconductor Packaging
Rayane Mazari serves as a Technology & Cost Analyst, Semiconductor Packaging, at Yole SystemPlus.
Rayane’s mission is to aid in the development of reverse engineering & costing reports. She works closely with the devices and laboratory team to set up significant physical & technology analyses of innovative IC and processor chips. She has a background in microelectronics.
Rayane holds a Master degree in Instrumentation & Microelectronics Engineering from Aix Marseille University.
Bilal Hachemi, PhD
Technology & Market Analyst, Semiconductor Packaging
Bilal Hachemi, PhD is a Technology & Market Analyst, Semiconductor Packaging at Yole Group.
Working within the Manufacturing & Global Supply Chain activities at Yole Group, he contributes on a day-to-day basis to the analysis of packaging technologies, their related materials and manufacturing processes.
Previously, Bilal carried out experimental research in the field of nanoelectronics and nanotechnologies, focusing on emerging dielectric materials and their ferroelectric applications. He (co-) authored several papers in high-impact scientific journals and was participated in several international conferences.
Bilal obtained a PhD in nanoelectronics in 2022 from the Grenoble Alpes university (France) and he studied at IAE Grenoble for a management master degree.
Gabriela Pereira
Technology & Market Analyst, Semiconductor Packaging
Gabriela Pereira is Technology & Market Analyst, Semiconductor Packaging at Yole Group.
Working within the Manufacturing & Global Supply Chain activities at Yole Group, Gabriela focuses on advanced packaging platforms, develops technology & market reports, and is engaged in dedicated custom projects.
Gabriela’s experience in the semiconductor field includes working at Amkor Technology, first for her master’s thesis and then as a R&D Engineer, where she collaborated on several package development projects.
Gabriela holds a master’s degree in metallurgical and materials engineering from the University of Porto, Portugal.
Stefan Chitoraga
Technology & Market Analyst, Semiconductor Packaging
Stefan Chitoraga is Technology & Market Analyst, Semiconductor Packaging at Yole Group.
Within the Manufacturing & Global Supply Chain activities at Yole Group, Stefan is focused on advanced packaging platforms and processes, substrates, and PCBs. He is involved daily in the production of technology & market products and custom consulting projects.
Prior to Yole Group, Stefan served as a package design engineer at Teledyne E2V for 4 years, where he oversaw the ceramic package and glass lid development for image sensors, developing mechanical design, routing, electrical and thermal simulations. Furthermore, he spent 2 years at STMicroelectronics where he developed a new IC Substrate design, for organic package for SerDes applications.
Stefan holds a Bachelor’s in electronics and computer science for industry applications from the Polytech Grenoble (France).
