High-end performance packaging industry: who are the winners and losers?

Product Related

High-performance computing and ADAS are driving the growth of high-end performance packaging, requiring multiple platforms for new technologies.


  • High-end performance packaging will be a US$7.87 billion market by 2027, with a 19% CAGR 2021-2027.
  • UHD FO , HBM , 3DS, and active Si interposer combined are forecast to comprise more than 50% of the high-end performance packaging market by 2027.
  • High-end performance packaging is creating waves of disruption in the semiconductor supply chain.

The market research and strategy consulting company, Yole Intelligence, part of Yole Group, has a comprehensive understanding of the semiconductor packaging industry. The company publishes an impressive collection of analyses, including technology & market reports, quarterly market monitors, and teardowns throughout the year.
Today, Yole’s semiconductor packaging team releases its annual high-end performance packaging report, High-End Performance Packaging 2022 – Focus on 2.5D/3D Integration. This new study analyzes in detail the challenges and opportunities of this industry. It provides market data on key high-end performance packaging technologies and delivers a valuable understanding of the value chain, infrastructure, and competitive landscape.

Stefan Chitoraga Technology and Market Analyst specializing in Packaging and Assembly at Yole
“In 2021, CapEx investments of about US$11.6 billion were made in package activity by the top players. Indeed, they are conscious about the enormous importance of fighting the slowdown of Moore’s Law and are adapting their strategies in that direction.”

Intel is the top investor, with US$3.5 billion. Its 3D chip stacking technology is Foveros, which consists of stacking a die on an active silicon interposer. An embedded multi-die interconnect bridge is its 2.5D packaging solution, utilizing a 55-micron bump pitch. The combination of Foveros and EMIB gives birth to Co-EMIB, used for the Ponte Vecchio GPU. Intel plans to adopt hybrid bonding technology for Foveros Direct.

Titre du visuel

june 2021

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Thematic(s) :

The other leader, TSMC, is following through with US$3.05 billion of CapEx. While securing more business for UHD FO with its InFO solutions, TSMC is also defining new system-level roadmaps and technology for 3D SoC. Its CoWoS platform offers solutions such as RDL or silicon interposers, while its LSI platform is a direct competitor for EMIB. TSMC has emerged as a high-end packaging powerhouse with leading FE advanced nodes allowing it to dominate next-generation system-level packaging.

Also on the podium, and boasting a US$2 billion estimated CapEx, ASE is the biggest and only OSAT trying to compete with the foundries and IDMs in packaging activity. With its FoCoS product, ASE is also the only OSAT with a UHD fan-out solution at the moment.
Yole’s analysts also identified Samsung, just behind ASE. Samsung has its I-Cube technology, which is similar to CoWoS-S. Samsung is one of the 3D-stacked memory solution leaders, providing HBM and 3DS. Its X-Cube will use hybrid bonding interconnects.
Today, OSATs don’t have the financial and front-end capabilities to keep pace with the big players like Intel, TSMC, and Samsung in the advanced packaging race. Therefore, they are followers.


  • CAGR : Compound Annual Growth Rate
  • UHD fan-out : Ultra High-Density fan-out
  • HBM : High Bandwidth Memory
  • Si : Silicon
  • EMIB : Embedded Multi-die Interconnect Bridge
  • Co-EMIB : Foveros (active Si interposer) + Embedded Multi-die Interconnect Bridge
  • GPU : Graphics Processing Unit
  • InFO : Integrated Fan-Out
  • SoC : System-on-Chip
  • RDL : Re-Distribution Layer
  • FE : Front-End
  • OSAT : Outsourced Semiconductor Assembly and Test
  • IDM : Integrated Device Manufacturer
  • FoCoS : Fan Out Chip on Substrate
  • CoWoS-S : Chip on Wafer on Substrate

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