Huawei Mate 60 Pro: what about the HiSilicon 9000s SoC?
Product Related
Discover all the technology ins and outs of the HiSilicon 9000s SoC in the Huawei Mate 60 Pro.
OUTLINE
What’s new?
The first SMIC 7nm (N+2) for a consumer product.
The first domestic advanced SoC from design to chip manufacturing in China.
From the newest generation Kirin 9000s, HiSilicon changed the SoC die manufacturer from TSMC to SMIC.
Near-term APU market revenue: sales increased in Q3/Q4 2023 as flagship smartphone launches spurred demand, and these used the highest-priced APUs .
With an estimated 43 million units shipped in 2023 – Mate 60 Pro included – Huawei gained 4% of the 1,150 million smartphone market in a single quarter.
HiSilicon, a fabless IC design company owned by Huawei, creates semiconductor chips for Huawei to support a wide range of smart devices, reports Yole Group. The Kirin series is the flagship model for high-end smartphones.
In 2020, HiSilicon unveiled the Kirin 9000 to power the Huawei Mate 40 Series. This chip was manufactured using TSMC’s 5nm technology. In 2023, Huawei introduced the Mate 60 Pro smartphone, featuring HiSilicon’s newborn SoC, the Kirin 9000s, as the main processor. The chip itself has the following dimensions: 14.5 x 14.3 x 0.4 mm3, with a 207 mm2 area and 0.35 µm ball pitch. It includes the HiSilicon Kirin 9000s SoC die package and DRAM package… What’s inside?
Yole Group releases today the technology, process & cost analysis/report, HiSilicon Kirin 9000s SoC in Huawei Mate 60 Pro. This analysis provides significant insights into the technical choices made by HiSilicon and the company behind it, the leading smartphone manufacturer, Huawei. This new report also delivers an insightful analysis of the manufacturing cost and selling price. Based on a complete Huawei Mate 60 Pro teardown available in Yole Group’s Consumer Teardown Tracks, Phone module, the HiSilicon Kirin 9000s SoC report reveals multiple details surrounding the processor and the integration of the LPDDR5 DRAM package atop the SoC die package on the main board. Indeed, it gives numerous analyses ranging from the SoC die FEOL and back-end construction to the assembly. With this new report, Yole Group’s analysts aim to provide an understanding of the technical breakthroughs and related manufacturing processes offered by the Chinese company HiSilicon. This new report highlights the top view and cross-section of the SoC using optical microscopy, CT-scan, SEM, and EDS to analyze the structure and materials. It also presents a complete analysis of SMIC’s N+2 FinFET using TEM. This report also offers a detailed comparative analysis of the Kirin 9000 and Kirin 9000s, encompassing packaging to SoC die characteristics and furnishes a complete cost analysis.
Ying-Wu Liu
Technology & Cost Analyst, Computing & Software at Yole Group
“At Yole Group, we confirm that the chip fabrication differs from HiSilicon’s previous solution, the Kirin 9000. Indeed, we assumed the 9000s SoC die has been developed and manufactured using SMIC’s N+2 (7 nm) process, with 13 metal layers.”
Titre du visuel
june 2021
You have to be registered to download our medias.
Usage restriction: Images may not be used against the interests of Yole Développement (Yole Group) and its entities, Yole Intelligence, or System Plus Consulting (Yole SystemPlus).
For more information, please contact the Public Relations team.
Licence
:
Images can be used online and for printing, without modification
Thematic(s)
:
For the DRAM package, two leading suppliers of LPDDR5 DRAM have been identified in Yole Group’s analysis: SK Hynix and Samsung. In this analysis, Yole Group has focused on the SoC with an SK Hynix memory package. The DRAM package (0.45 mm) is stacked on the HiSilicon Kirin 9000s SoC die package (0.40 mm). The whole chip is assembled using PoP technology and then connected to the main board of the smartphone. PoP technology allows processor manufacturers to integrate DRAM packages from different suppliers. The DRAM package connects to the SoC die package using DRAM package balls. The SoC die package is connected to the main PCB using SoC package balls. It consists of a top substrate with an embedded layer and a bottom substrate. The copper core solder balls in the embedded layer are used as an electric connection between the top and bottom substrates. The SoC die is integrated into the embedded layer and flip-chipped onto the bottom substrate. According to Yole Group’s analysis, there are twelve metal layers in the main PCB… More details are available in Yole Group’s analysis.
In 2023, we saw with the Mate 60 Pro that there is a complete substitution of U.S. devices and a significant reduction in Japan-sourced devices as well. Domestically sourced devices from mainland China now make up 50% of the design win count; more importantly, they comprise the most critical components of this premium segment phone. Learn more by reading the full article From Mate 30 Pro 5G to Mate 60 Pro: a Technology Path from China, written by Yole Group’s Principal Analyst Global Semiconductors Pierre Cambou.
Yole Group’s computing and software team invites you to follow the technologies, related devices, applications, and markets on www.yolegroup.com.
In this regard, make sure to attend IMAPS DEVICE PACKAGING CONFERENCE – DPC from March 18 to 21. Do not hesitate to ask for a meeting with our experts at Image Sensor Europe: HERE.
Ying-Wu Liu Technology & Cost Analyst, Computing & Software at Yole Group“At Yole Group, we confirm that the chip fabrication differs from HiSilicon’s previous solution, the Kirin 9000. Indeed, we assumed the 9000s SoC die has been developed and manufactured using SMIC’s N+2 (7 nm) process, with 13 metal layers.”
