Technology, Process and Cost
DBI Process in Jasminer X4-Q Mining ASIC
By Yole SystemPlus —
China’s 3D Integrated Circuit using hybrid bonding interconnection technology between DRAM and logic die
SPR23760
Overview
- Executive Summary
- Product Specification
- Reverse Costing Methodology
- Glossary
Company Profile
- Sunlune
Physical Analysis
- Summary of the physical analysis
- Jasminer X4 Board Teardown
- ASIC Package & Die
- Logic Die Analysis ( Cross Section, Delayering)
- DRAM Die Analysis ( Cross Section, Delayering)
Manufacturing Process Flow Analysis
- Global Overview
- DRAM Die Front-End Process & Wafer Fabrication Unit
- Logic Die Front-End Process & Wafer Fabrication Unit
- Hybrid Bonding & Passivation
- Packaging process
Cost Analysis
- Cost Summary
- Yields Explanation & Hypotheses
- DRAM Die Front-End Wafer Cost
- Logic Die Front-End Wafer Cost
- Hybrid bonding & Passivation Cost
- Die Cost
- Packaging Cost
- Component Cost
Feedbacks
Related Products
About Yole Group
Direct hybrid bonding between logic & DRAM wafer
China is racing to keep up with ‘made in China’ semiconductor strategy and goal by staying innovative in different semiconductor manufacturing processes. Artificial Intelligence is growing widely, and Chinese manufacturers have positioned themselves to support the digital economy by developing advanced semiconductor processes that can expand computing power to support development of artificial intelligence and generation and storage of huge amounts of data being produced. The supply chain is being structured to rely mainly on the Chinese OEM.
SunLune broke through with an innovative ASIC chip based on the new 3D IC technology platform. This incorporates a logic die and DRAM die bonded together through copper-to-copper hybrid bonding to increase chip bandwidth. With its leading 3D integrated and high-throughput ASIC, Sunlune designed this chip targeting the crypto world. This chip enables high throughput, high computing power and low power consumption in crypto mining applications thanks to the new 3D IC architecture.
Hybrid bonding has been introduced a few years back in the semiconductor industry, this type of heterogenous integration solves the problem of using conventional bumps that have spacing limitations. Hybrid Bonding also has unique advantages in electrical performance, lower signal loss which is important to manage in high-performance computing applications. In this architecture and technology, the bandwidth gap between the logic die and the memory is reduced, resulting in faster communication between the dies. Analysis of this component shows the IC logic stacked on the DRAM die, the direct bond interconnect achieves pad pitch of less than 5µm, and denser interconnection compared to microbumps.
This full reverse costing study has been conducted to provide insight on technology data, manufacturing cost and selling price of the Jasminer X4 ASIC component. To reveal all the details of the Jasminer X4 , this report starts with a teardown of Jasminer X4Q-840M server. The report equally features multiple analyses from FEOL of the logic and DRAM die, as well as a back-end construction analysis for ASIC packaging structure. This report also includes a detailed study of the die and its cross-sections focusing on the Copper to Copper hybrid bonding interconnections. Lastly, this report furnishes a complete cost analysis and a selling price estimation.
- Wuhan Xinxin Semiconductor Manufacturing Co., Ltd.(XMC)
- Xi'an UnilC Semiconductors Co
- Sunlune
- Jasminer
Key Features
- Detailed photos
- Precise measurements
- Materials analysis
- Manufacturing process flow
- Supply chain evaluation
- Manufacturing cost analysis
Product Objectives
- Physical and cost analysis of the hybrid bonded logic and DRAM die making the Jasminer ASIC