YMTC 232-layer 3D NAND Memory

Overview  

• Executive Summary
• Reverse Costing Methodology
• Glossary

Company Profile  

• YMTC timeline
• NAND Evolution & YMTC Products
• Xtacking Technology
• Market Analysis

Physical Analysis 

• Summary of the physical analysis
• Package Analysis (X-Ray Images, Cross section, Opening)
• Die Analysis (cross section, process)

Physical Analysis Comparison 

• Package, Memory die, Die Cross section, Bonding & CMOS Technology

Manufacturing Process Flow Analysis 

• Global Overview
• CMOS & Memory Die Front-End Process
• CMOS & Memory Die Front-End Wafer Fabrication Unit
• Packaging process

Cost Analysis 

• Cost Summary
• Yields Explanation & Hypotheses
• CMOS & NAND Array Front-End Wafer Cost
• Bonding Cost
• TSV & Top Metal Cost
• Bonded Wafers Cost
• Memory Die Cost
• Packaging Cost
• Component Cost
• Cost per GB/Gb

Selling Price  

• Definitions of Price
• Manufacturer Financials
• Estimated Selling Price

Related Products 

About Yole Group  

Key Features

• Detailed photos
• Precise measurements
• Materials analysis
• Manufacturing process flow
• Supply chain evaluation
• Manufacturing cost analysis
• Physical analysis comparison between YMTC’s 232-layer, 128-layer and 64-layer NAND Memory

What's new

• New generation memory with a total of 232 active wordlines
• Denser pads and reduced pad pitch
• Reduced wordline layer thickness
• Reduced insulating oxide layer thickness

• Yangtze Memory Technologies Corp (YMTC)

Total NAND memory market revenue dropped by 12% in 2022, from $66 billion in 2021 to $59 billion in 2022. Yangtze Memory Technologies Corp (YMTC) is the leading memory designer and manufacturer in China. In 2022, YMTC rolled out its groundbreaking 200+ layer NAND memory, reaching this milestone before its competitors.

Xtacking is an innovative technology introduced by YMTC. It involves bonding two wafers together. The NAND array wafer is hybrid bonded to the Complementary Metal Oxide Semiconductor (CMOS) wafer. The copper metal pads from each wafer become the bonding interface. This technology proves to be a cost-effective scaling method providing the market with high performing NAND memory. YMTC introduced the Xtacking 3.0, which it claims has 50% improved performance compared to Xtacking 2.0. It also reduces power consumption. The 232-layer NAND dies from YMTC increased die density by more than 80% compared to the 128-layer NAND die.

This full reverse costing study provides insights regarding the technology data and manufacturing cost of YMTC’s 232-layer 3D NAND memory. This report provides optical and high-resolution scanning electron microscopy (SEM) cross-section images of the NAND memory die. Multiple analyses reveal important details of 232-layer NAND memory chip. This includes the front-end construction, detailing the CMOS transistors and their metal layers, followed by the NAND array structure, metal layer and interconnections. The hybrid bonding is analyzed in detail that includes the bonding interface and copper pad pitch. The six plane 128GB NAND memory die also uses through silicon vias in its process. Finally, the back-end construction analysis shows the chip integration in the package.

In the report, the 232-layer NAND memory is compared to its predecessors, the 128-layer NAND memory and the 64-layer NAND memory from YMTC, the physical comparison includes package comparison, NAND dies, NAND array features, bonding region and finally the CMOS process.