YMTC 232-layer 3D NAND memory: an unexpected technological breakthrough – The chronicles by Yole SystemPlus

In Q4 2022, YMTC launched its fourth-generation 3D NAND memory. Only three years after introducing its second-generation chip using a 64-layer package, the Chinese manufacturer has staged a technological coup and broken a record with the release of a new device featuring 232 wordline layers and the highest storage density ever.  However, the state of the global memory market and tension between China and the US are a fly in the ointment for YMTC.

At first sight, manufacturing 232-layer NAND dies with good yields seems very complex. How did YMTC pull off this feat? This piqued the curiosity of Yole SystemPlus, part of Yole Group, which had already its eye on the Chinese manufacturer’s devices from the beginning. In its latest report – YMTC 232-layer 3D NAND Memory – the company, part of Yole Group, provides insight into the entire manufacturing process and reveals the secrets behind YMTC’s Xtacking® architecture. A comparison of the key features of the die with the 64-layer and 128-layer packages is also included.

In its Status of the Memory Industry report, Yole Intelligence asserts that over the past several quarters, the memory markets have faced the most dramatic downturn of the last 15 years. NAND average selling prices (ASPs) have fallen 55% since Q3-2021 reaching $0.05/GB in early 2023.

The most severe decline started in the final weeks of Q2-2022, when a perfect storm of demand-side developments (global conflicts, high inflation, China COVID lockdowns, etc.) crashed into the memory markets.

In addition to the market collapse, YMTC has also been facing strong headwinds due the commercial restrictions set in October 2022 by the U.S. Department of Commerce (DoC); the new rules require U.S. vendors to obtain a license to ship and support 128L-and-above NAND equipment to producers that operate in China.

Despite the very challenging context, YMTC has accomplished significant progress.

Xtacking architecture: YMTC’s NAND memory centerpiece

At the very heart of the manufacture of all YMTC’s 3D NAND chips is the Xtacking approach. Known as YMTC’s hallmark, Xtacking involves the use of two separate wafers, whereas only one wafer is traditionally employed. It consists of building the NAND dies by joining a CMOS wafer and a NAND array wafer face to face, the two wafers being bonded together using metal pads. Both wafers can be manufactured simultaneously, enabling the manufacturer to shorten the production cycle in case of high memory demand.

A cross-sectional view of the die shows that two decks of alternating tungsten wordlines and SiO layers are formed one after the other. This method was adopted to reduce high aspect ratio etching. If built in one deck, the etch channel aspect ratio would have been 109:1, which would have resulted in very complex trench etching and filling processes and a higher etch defect number.

The strategy is always to find the right balance between yield losses and the cost induced by repeating the etching process. Two hundred fifty-three wordlines are observed in the vertical NAND string; 128 layers form Deck 1 and 125 form deck 2. Besides the 232 active layers, the remaining ones are divided between dummy and selection layers.

Yole SystemPlus identified the use of a hybrid direct bonding technique to build chemical-free copper-to-copper interconnects that join the wafers together introduced by YMTC in memory manufacturing. Physical interaction between the dielectric material and the copper metal from the two wafers forms a strong bond. The bonding interface is further strengthened by plasma treatment of the surfaces and a thermal/annealing process. With this technique, YMTC is able to scale the bonding pad pitch down to 0.8 µm. In addition, accurate pad alignment is observed, with a pad mismatch of 22 nm representing only 6% of the pad surface.

Key features and comparative analysis of 232-layer 3D NAND memory

As a result of increasingly mastered Xtacking technology, YMTC’s fourth-generation memory chip features faster I/O transfer speed and higher storage density. The stacked design combined with a minimized bonding pad and word-line pitches has enabled YMTC to improve storage density by a factor of 3.5 since the second generation of dies. At 15.47 Gb/mm2, the 232-layer NAND chip surpasses Samsung and Micron 176-layer 3D NAND which only reach 10.9 Gb/mm² and 10.29 Gb/mm², respectively.

The die area has not changed much (an increase of around 5 to 10%) for a capacity that has doubled from one generation to the next (32, 64, and 128 GB). As the number of layers has doubled, it was expected that the die thickness would be doubled too. What was true from generation 2 to generation 3 (4.4 µm versus 8.6 µm) is not the rule for generation 4 (11.9 µm). To minimize the total height of the stack, YMTC has reduced the wordline pitch by 20% compared to the previous generation.

Facing economic turmoil

Seen as a threat by the major players, YMTC does not yet have a significant market share. Despite its meteoric rise since its creation in 2016 and technological edge, YMTC is still fighting against the historical players including Samsung, SK hynix, Micron Technology, Western Digital, and Kioxia and is bearing the brunt of bilateral trade tensions with the US.

About to finalize a major contract with Apple, the Chinese manufacturer was registered on the US Entity List last December (like Huawei three years earlier). Furthermore, the memory industry has been facing a severe downturn for a year now, which is expected to continue into the second half of 2023, according to Yole Intelligence.

How long will the additional funding, provided this year by both private investors and the Chinese government enable YMTC to keep its head above water?

Stay tuned on to follow this industry and get a deep understanding of YMTC’s strategy!

Related event


Once again, Yole Group will be part of the Flash Memory Summit experience as exhibitor – booth#949 – and we are very glad to get the opportunity to meet our customers and business partners, establish new contacts in the industry and help drive your business forward.

Simone Bettolazzi, Senior Technology and Market Analyst, Memory, Mike Howard, VP of DRAM and Memory Research, and Walt Coon, VP of NAND and Memory Research, from Yole Intelligence, along with Belinda Dude, Technology and Cost Analyst, Memory from Yole SystemPlus, will take part of this all-inclusive international memory and storage showcase.

It is the one-stop place to catch up on the latest technologies, see the hottest products, and learn about what’s happening and where the latest trends are heading. FMS is now the largest memory and storage industry show with the most high-level keynoters from leading companies, the largest exhibits, and the most sessions covering everything from applications and architectures through enterprise storage, controllers, and new technologies.

Come, meet Yole analysts and look through our latest market, technology, reverse engineering and reverse costing analysis with direct discussion with Yole memory analyst team !
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About the authors


Belinda Dube is a Technology & Cost Analyst at Yole SystemPlus, part of Yole Group. Belinda’s core expertise is memory technology, especially DRAM and 3D NAND flash memory. At the same time, she also investigates IC technologies as well as advanced packaging. Belinda’s mission is to develop reverse engineering & costing reports. She also works closely with the laboratory team on custom projects, setting up relevant physical & chemical analyses of innovative memory chips. Based on the results, Belinda identifies and analyzes the overall manufacturing process and all technical choices made by the memory makers. The objectives of these analyses are to understand the structure of the device, identify all materials used, and point out the link between functionality and technology selected by the memory company. In addition, a significant portion of Belinda’s mission is dedicated to a strategic technology watch, where her aim is to identify innovative memory chips and manufacturing processes. Based on her expertise, Belinda updates internal simulation tools and runs custom training sessions and demos with industrials. Belinda attends many international trade shows & conferences where she collects valuable information and meets leading memory players. She regularly has an opportunity to reveal pertinent results during key onsite presentations and webcasts. Prior to Yole SystemPlus, Belinda had the opportunity to work on several R&D projects on MEMS technologies and new substrates at INSA (Lyon, France). Belinda holds a master’s in Instrumentation & Nanotechnology Engineering from INSA (France).


Simone Bertolazzi, PhD, is a Principal Technology & Market Analyst, Memory, at Yole Intelligence, part of Yole Group, working with the Semiconductor, Memory & Computing division. As member of Yole’s memory team, Simone contributes on a day-to-day basis to the analysis of memory markets and technologies and their related materials, device architectures, and fabrication processes. Previously, Simone carried out experimental research in the fields of nanoscience and nanotechnology, focusing on emerging semiconducting materials and their opto-electronic device applications. He obtained a PhD in Physics in 2015 from École Polytechnique Fédérale de Lausanne (Switzerland), where he developed novel flash memory cells based on heterostructures of two-dimensional materials and high-κ dielectrics. Simone also earned a double M. A. Sc. degree from Polytechnique de Montréal (Canada) and Politecnico di Milano (Italy), graduating cum laude.