The devices that handle most of the computing needs of today’s consumers are either smartphones, tablets, or personal computers (PC). In terms of shipped quantity, smartphones take the lion’s share, with more than three times the amount of annual shipments as tablets, laptops, and desktops combined, according to Yole Développement’s market data.
In terms of value to processor vendors, however, the playing field is a little more balanced, as desktop and laptop processors generated over $40 billion for chipmakers in 2021 versus $37.8 billion for smartphones. Underlying this is the difference in applications, of course, but more specifically there is the difference in instruction set architecture. Smartphones and tablets are mainly the domain of Arm-based processors. The PC environment has largely been the domain of x86-based processors, but recently we can start to see more and more blurring of this trend.
With little exception, high-end PCs have run on x86-based processors, primarily the domain of Intel and AMD, while Arm-based architecture deployment was limited to a subset of ultra-light PCs and Chromebooks. The tectonic shift initiated by Apple’s M1 project is a major proof that high-end PCs can be successfully run on Arm-based architecture. Apple’s M1 showed that this architecture can compete in mainstream consumer platforms in both power consumption and performance.
The impact on the technological makeup of the market has been profound, as from 2019 to 2021, Arm-based processors in PCs increased almost seven-fold, predominantly due to Apple’s shift to in-house processors for Mac. With the upgrades of the M1 Pro and M1 Max and eventually the M1 Ultra, Apple is showcasing the remarkable scalability of their project and inviting industry observers to dream of what could come next, much like the company has done time and again in the smartphone arena.
System Plus Consulting and Yole Développement (Yole) have followed Apple and its activities closely for a while. Both partners investigate the technology choices made by this leading smartphone manufacturer and have taken a step back to analyze in-depth the impact on the mobile industry. Today, our analysts provide you with a snapshot of Apple’s latest innovations and remind you of the underlying industrial context. This analysis is extracted from the Apple M1 Max System-on-Chip and Apple M1 Pro System-on-Chip reports and the Processor Quarterly Market Monitor.
As upgraded versions of the Apple M1 system-on-chip (SoC), the M1 Pro and Max massively expand the die size, complexity of IP design, and even physical structure. By measuring the SRAM size and the gate/fin pitch from high-resolution SEM photos, we confirm that the M1 Pro and M1 Max SoC dies are both manufactured in TSMC’s 5nm Fin Field-Effect Transistor (FinFET) technology, the TSMC N5P process which has the same design rule as the original N5 platform. While keeping the same finFET structure and SRAM density, we observe from the die cross-section that both the M1 Pro and Max have the same metal interconnect stack but more levels than the previous M1. The configuration of the final product assembly is the same as the first M1 generation. The M1 Pro and M1 Max both include one SoC die and LPDDR5 DRAM memory packages. To be more specific, the M1 Pro includes two LPDDR5 components, while the M1 Max has four.
Apple continues to use memory components from various suppliers. Our teardown of multiple MacBook Pro units revealed memories supplied by both Samsung and Hynix. Since the DRAM providers are all building to the same standard, the final assembly is manufacturer agnostic. Regarding the overall product assembly, system-in-package (SiP) technology is applied to both the M1 Pro and Max – the SoC die shares the same substrate with DRAM packages and multilayer ceramic capacitors (MLCCs) while several integrated passive devices (IPDs) are embedded in the backside of the substrate. The whole chip assembly ends with an integrated heat spreader (IHS) on the top while the bottom is soldered to the mother board which is shared with other components and power modules, using a ball grid array (BGA).
The first Apple-branded processor was the A4 that powered the original iPad. However, a relatively small contribution from the newly formed Apple silicon design team was evident on that processor. The first full Apple design was the next iteration of Apple Ax mobile processors, the A5. In terms of manufacturing technology, these were both produced on the Samsung 45 nm platform.
Although in-house Apple silicon designs in the 5nm process were old news with the A14 in the iPhone 12 and A15 in the iPhone 13, the launch of the first Apple processor for personal computers – the M1 – managed to shock the industry.
The M1 was a good introduction for entry-level MacBook Airs and Mac minis. In system benchmark tests, the M1 performed well. From a high-altitude vantage point, the M1 included a quad-core high-performance compute cluster, a quad-core efficient compute unit, and an eight-core graphics processing unit (GPU).
Apple’s silicon design team has now expanded the M1 line into the realm of the professional user demanding much more computing power. Near the end of last year, Apple launched the M1 Pro and M1 Max generations of their processor line. More recently, the M1 Ultra was announced to round out a product line to address everything from serious amateurs to the most demanding professional applications like video editing.
The latest processors from Apple have obviously come a long way from the first A4 and A5 mobile applications processors on 45 nm process technology to today’s devices on the most advanced 5 nm finFETs from TSMC.
But the Apple story is more about the strides made by their own design team rather than their silicon vendor.
Apple has developed a scalable strategy with the newest M1 designs to address a wide range of use cases. The M1 Pro is the lowest end of the scale, but as far as compute cores are concerned, the Pro and Max share the same design. Both versions include a total of 10 computing cores. In a departure from the original M1, there are now eight high-performance cores and two efficiency cores.
When Apple first announced the original M1, it highlighted the Unified Memory Access (UMA) feature. Memory access is critical and is definitely part of the scalability story. Apple specifications indicate that the M1 Pro design can access up to 32 GB of LPDDR5 DRAM, while the Max design doubles this to 64 GB. As Apple’s senior vice president of Hardware Technologies, Johny Srouji, never hesitates to point out, the M1 Pro and Max designs are the first system-on-chip designs for pro computer systems. And unified memory offers advantages over conventional designs by giving the GPU quadruple the amount of memory access compared to competing PC laptop designs. Speaking of the GPU, this aspect of the newest Apple silicon is a giant leap beyond the original M1. The M1 Pro features double the cores at 16, with the M1 Max doubling again to 32.
According to Apple, the M1 Max also doubles the memory bandwidth of the Pro. The M1 Max provides up to 400 GB /s. In many cases, the floorplan of the Max is also double. This is an obvious case for the memory bandwidth as the Max contains twice as many LPDDR5 DRAM access channels, and as noted previously, the final product has double the number of LPDDR5 components.
The Max version of M1 doubles other functionalities compared to the Pro as well. The M1 Max includes two instances of the 16-core neural processing unit (NPU) found on the Pro. A total of four image signal processing cores appears on the Max compared to just two in the Pro version. Likewise, the system SRAM cache doubles in size.
Beyond just dropping in repeated instances of circuit blocks of the M1 Pro to increase functionality, there is one significant area of circuitry exclusive to the M1 Max. This is the high-speed parallel die-to-die interface. Since there is no second die to communicate with in the M1 Max product, this might seem a little odd. But this is where the M1 Ultra makes its entrance.
The M1 Ultra is a multi-chip assembly of two M1 Max dies. To enable a fully functioning processor of double the capability of the M1 Max, a high bandwidth interface to connect two M1 Max dies is a critical design feature. Despite the M1 Max not communicating with another die, the design includes the die-to-die interface that allows the same silicon to be used for Max-only products as well as assembled into the Ultra configuration.
So, what’s next?
Apple upped its game in the personal computer microprocessor realm with two versions of a new design aimed at professional-grade laptops.
The M1 Max is the largest chip Apple has ever designed. With the implementation of the die-to-die interface and tiling multiple Max dies together, the M1 Max could well be the largest design Apple will ever produce. But taken together, the product family of M1 Pro, Max, and Ultra show an Apple strategy focused on ease of scalability to target specific applications.
System Plus Consulting and Yole Développement will pursue their investigations and invite you to stay tuned for future teardowns and market analyses!
About the authors
Ying-Wu Liu is a Technology & Cost Analyst at System Plus Consulting, part of Yole Développement. Ying-Wu ’s core expertise is Integrated Circuit technologies.
With solid expertise in physical and electronic analyses of devices and experience in wafer manufacturing and technical support with international clients, Ying’s mission is to develop reverse engineering& costing reports.
Prior to System Plus Consulting, Ying worked as Technical Support Manager at KEOLABS, where she had the opportunity to build up her ability to cooperate with clients from different cultures.
Ying holds a master’s degree in Theoretical Physics from the National Tsing Hua University (Taiwan) and a master’s in Integration, Security and Trust in Embedded systems from the Grenoble INP, ESISAR (France).
As an External Analyst, Don Scansen has partnered with System Plus Consulting to launch the new die architecture and front-end process analysis of advanced SoC devices, including APU, CPU, GPU, and FPGA. Don previously supported clients ranging from individual patent owners to Fortune 500 companies providing competitive analyses and intellectual property support.
Don holds a Ph.D. in electrical engineering.
John Lorenz is a Senior Technology and Market Analyst, Computing & Software, within the Semiconductor, Memory & Computing division at Yole Développement (Yole), part of Yole Group of Companies. John is engaged in the development of market and technology monitors for the logic segment of advanced semiconductors, with an initial focus on processors. Prior to joining Yole, John held various technical and strategic roles at Micron Technology.
On the engineering side, John’s roles included thin film process development and manufacturing integration on DRAM, NAND, and emerging memory technologies and industrial engineering / factory physics for the R&D fab.
On the strategic side, John ran the memory industry supply & Capex model for corporate strategy / market intelligence and established the industry front-end costing model within strategic finance.
John has a Bachelor of Science degree in Mechanical Engineering from the University of Illinois Urbana-Champaign (USA), with a focus on MEMS devices.
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