Electroplating silicon TSV: a closer look…

We have been hearing about the drilling and filing of silicon TSV for more than a decade, but every once and awhile a new approach comes along. Professor Kazuo Kondo from the Osaka Prefecture University works in the Small Feature Electrodeposition Laboratories and has been looking to reduce the cost of copper electrodeposition in silicon TSV. i-Micronews thought Kondo-sans work was worthy of… a closer look.

Conventional Bosch Etching for silicon TSV results in relatively straight walls, but results in a relatively slow electrodeposition fill. Professor Kondo is looking at filling conical vias created by non Bosch processes. Recently they have achieved a 30 sec or less electrodeposition time for a 2 x 16µm TSV which are typical of what much of the industry is looking for. The slope on these TSV is 87-88 deg. The barrier is a proprietary vapor deposited, thermally stable, polymer liner. As plated the copper resistance is high, but,as in regular plating, after anneal the resultant larger grains produce bulk copper resistance. The cross section shows no voiding typical of many Bosch via electrodeposition fills.

2×16μm via filling within 30 seconds
[Source: K. Kondo private communication – June 2016]

Shortening of electrodeposition time eliminates some of the initial investment for electrodeposition equipment and at the same time, reduces the clean room area required for the fewer required electrodeposition tools.
They are working on commercial equipment development with Tozetz, a manufacturer of back end electroplating equipment in Japan. They are also in partnership with ULVAC and their fast etching process to provide a complete drill and fill solution. The exact nature of the processing that speeds up the deposition is currently not being revealed.
The Kondo-san group in Osaka is also looking into eliminating so called “copper pumping”. The use of silicon vias (TSVs) causes copper extrusion due to the mismatch of the thermal expansion coefficient of copper and silicon. This extrusion can cause damage to the interconnect above it as shown in the figure below. The current technology for avoiding this damage is to anneal the TSV at > 425 °C and then CMP the resultant copper protrusions before building the layers of on chip interconnect.

Cross sectional view of copper pumping damage [Source: K Kondo private communication – June 2016]

The Small Feature Electrodeposition Lab has developed an additive “A”, which restricts the copper pumping phenomena. A comparison of pumping with and without additive A at 450 °C is shown below.

Pumping at 450 °C (a) room temp; (b) without additive “A” at 450 °C ; (c) room temp ; (d) without additive “A” at 450 °C [Source: K Kondo private communication – June 2016]

The resistivity of electrodeposited copper TSV after 450? annealing for the wiring is only 1.09 of conventional electrodeposited copper. Initial investigations of the mechanism of this reaction point to 100nm carbon deposition into the triple point of the copper grains.

From Dr. Phil Garrou for Yole Développement

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