EPTC: IEEE CPMT Society’s flagship conference in Asia Pacific Region

Special rate apply for PDC group registration. Please contact the conference secretariat HERE for group registration

Books Giveaway: With the support from our Partnering Publisher, we are giving away high quality microelectronics packaging related book to early registrant. The first ten conference registrant or the first registrant for each PDC will be entitle for a book.

ABOUT EPTC

The 18th Electronics Packaging Technology Conference is an International event organized by the IEEE Reliability/CPMT/ED Singapore Chapter and sponsored by IEEE CPMT Society. EPTC 2016 will feature:

• Technical Sessions
• Short Courses (PDC)/ forums
• Exhibition (booth are available and prospectucs is available HERE)
• Social and networking activities
• Heterogeneous Integration workshop

PROFESSIONAL DEVELOPMENT COURSES

The conference program includes short courses (30 Nov 2016), which will be conducted by leading experts in the field.

• James E. Morris (Portland State University): “Nanotechnologies for Microelectronics PackagingApplications:Current trends in IoT, Wearable, 3D, Flex Circuits, Thermal and Embedded passives”
• Ingrid De Wolf (IMEC): “3D Integrated Failure Analysis”
• Albert Lan(SPIL): “Fan-In and Fan-Out in Wafer Level Packaging”
• Yogendra Joshi(Georgia Tech): “Energy Efficient Thermal Management of Data Centers”
• Holden Li(NTU):” Internet of Things (IoT) focusing on Wireless Sensors Network and Active RFID”
• Paul D. Franzon(NCSU): “2.5D- and 3D-Stacked Integrated Circuit”

PDC details can be found here.

CONFERENCE TOPICS

• Advanced Packaging: Flip-chip, multiple array leadframe package, POP, System in Packaging, etc. TSV/Wafer Level Packaging: Fan-in/Fan-out, embedded chip packaging, 2.5D/3D integration, TSV, Silicon & Glass interposer, RDL, bumping technologies, etc.
• Interconnection Technologies: Au/Ag/Cu/Al Wire-bond technology, Flip-chip & Cu pillar technology, solder alternatives, Wafer level bonding & die attachment etc.
• Emerging Technologies: Packaging technologies for MEMS, biomedical, optoelectronics, Internet of things, photo voltaic, printed electronics, wearable electronics, Photonics, LED, etc.
• Materials and Substrates/Leadframes: from polymer to solder materials, and Substrates / Interposer /Leadframes / PCB etc.
• Processes and Automation/Equipments: new process as well as equipment automation development.
• Electrical Modeling & Simulations: Power plane modeling, signal integrity analysis of substrate/package.
• Mechanical Modeling & Simulations: Thermo-mechanical, moisture, fracture, fatigue, vibration, shock and drop modeling, Chip-package interaction, etc.
• Thermal Characterization & Cooling Solutions: Component, system and product level thermal management, characterization and simulation
• Quality & Reliability: Component, board, system and product level reliability assessment, Interfacial adhesion, accelerated testing, failure characterization, etc.
• Wafer/Package level & TSV Testing and Characterization: High-speed test architectures and systems design, 2.5D & 3D test methodologies, probe card design, package-test interaction, high-throughput testing etc.

PANEL TOPIC HIGHLIGHTS

Title: “Rise of China Semiconductor” Topics: Semiconductor industry statistics and projections in China, Government policies, Supply chain, Semiconductor manufacturing and Packaging technologies, Opportunities & Challenges for China and for other countries/areas.

Ranjan Rajoo, General Chair
Xueren Zhang, Technical Chair

Source: https://eptc-ieee.net